JPS5637895A - Control method of memory unit - Google Patents

Abstract

PURPOSE: To prevent malfunction caused by an unspecific pulse by widening the pulse width of an input pulse to a fixed value or more when the input pulse is detected at a fixed threshold level in the operation effective period of a memory element.

CONSTITUTION: Pulses 4 and 5 generated on the chip enable line extending from AND circuit 10₁ are recognized by comparator 52. A pulse exceeding the threshold level of this comparator 52 is passed through OR circuit 53, whose output is timed fixedly by timer 54 and the timing pulse returned to OR circuit 51 and CE timing in normal operation are OR-ed to obtain chick enable timing. With this timing, memory elements 11W14 are placed in the disenable state through circuit 10₁. For a decision on the state, on the other hand, this timing and an inverted signal from NOT circuit 55 as to normal CE timing are AND-ed by AND circuits 56₁W56₄ and when the both agree mutually, an output is generated by OR circuit 57 to permit a timing error to be recognized externally.

COPYRIGHT: (C)1981,JPO&Japio