JPS55154605A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS55154605A
JPS55154605A JP6226679A JP6226679A JPS55154605A JP S55154605 A JPS55154605 A JP S55154605A JP 6226679 A JP6226679 A JP 6226679A JP 6226679 A JP6226679 A JP 6226679A JP S55154605 A JPS55154605 A JP S55154605A
Authority
JP
Japan
Prior art keywords
circuit
signal
level
output
failure detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6226679A
Other languages
Japanese (ja)
Inventor
Yutaka Hiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6226679A priority Critical patent/JPS55154605A/en
Publication of JPS55154605A publication Critical patent/JPS55154605A/en
Pending legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE: To enable normal control even if failures are continually taken place for a given time delaying the automatic initialization by taking the output of a failure detection circuit as L level.
CONSTITUTION: A failure detection circuit 2 detects a failure in a control operation section 1 and the output A is taken as logically L level. Further, an automatic initialization circuit 3 receives the L level signal and produces a signal shot pulse B by the trailing of the signal. On the other hand, when a delay circuit 4 of a failure detection signal A receives the signal A, that is, when the level of signal A is at L, the output C of the circuit 4 is at L level with a delay. In this case, the delay time is made longer than the pulse width of the single shot pulse produced in the circuit 3. Thus, if failures are continually taken place within a given time, the output C of the circuit 4 is delayed and the function of automatic initialization is blocked, enabling normal control.
COPYRIGHT: (C)1980,JPO&Japio
JP6226679A 1979-05-22 1979-05-22 Sequence controller Pending JPS55154605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6226679A JPS55154605A (en) 1979-05-22 1979-05-22 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6226679A JPS55154605A (en) 1979-05-22 1979-05-22 Sequence controller

Publications (1)

Publication Number Publication Date
JPS55154605A true JPS55154605A (en) 1980-12-02

Family

ID=13195164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6226679A Pending JPS55154605A (en) 1979-05-22 1979-05-22 Sequence controller

Country Status (1)

Country Link
JP (1) JPS55154605A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608901A (en) * 1983-06-29 1985-01-17 Tokai Rika Co Ltd Malfunction preventing method of load control device
JPS6446769A (en) * 1987-12-28 1989-02-21 Canon Kk Image processor
JPH01113703U (en) * 1988-01-28 1989-07-31

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608901A (en) * 1983-06-29 1985-01-17 Tokai Rika Co Ltd Malfunction preventing method of load control device
JPS6446769A (en) * 1987-12-28 1989-02-21 Canon Kk Image processor
JPH0565872B2 (en) * 1987-12-28 1993-09-20 Canon Kk
JPH01113703U (en) * 1988-01-28 1989-07-31

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