JPS55157040A - Failure recognition method for information processor - Google Patents

Failure recognition method for information processor

Info

Publication number
JPS55157040A
JPS55157040A JP6495479A JP6495479A JPS55157040A JP S55157040 A JPS55157040 A JP S55157040A JP 6495479 A JP6495479 A JP 6495479A JP 6495479 A JP6495479 A JP 6495479A JP S55157040 A JPS55157040 A JP S55157040A
Authority
JP
Japan
Prior art keywords
counter
failure
fed
production
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6495479A
Other languages
Japanese (ja)
Inventor
Masakazu Ariyasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6495479A priority Critical patent/JPS55157040A/en
Publication of JPS55157040A publication Critical patent/JPS55157040A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To enable the failure recognition taking into consideration the frequency of production of failures, by reducing the count value of the counter by a given number if the next failure is taken place after a given time, after the production of a failure.
CONSTITUTION: A counter 20 is a sort of timer circuit and it monitors whether the next failure production signals 10W12 are fed or not from the end of count operation of an up down counter 13 while a given time T is elapsed. If the signals 10W12 are absent even after the time T or more, FF21 is set and FF18 is set with "1" signal applied via the OR gate 26. Next, when one clock is fed to a shift register 19, an AND gate 13 is ON and FF18 is reset. Accordingly, one clock is fed to the counter 13. In this case, since the counter 13 is in count down state, count down is made by one.
COPYRIGHT: (C)1980,JPO&Japio
JP6495479A 1979-05-28 1979-05-28 Failure recognition method for information processor Pending JPS55157040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6495479A JPS55157040A (en) 1979-05-28 1979-05-28 Failure recognition method for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6495479A JPS55157040A (en) 1979-05-28 1979-05-28 Failure recognition method for information processor

Publications (1)

Publication Number Publication Date
JPS55157040A true JPS55157040A (en) 1980-12-06

Family

ID=13272933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6495479A Pending JPS55157040A (en) 1979-05-28 1979-05-28 Failure recognition method for information processor

Country Status (1)

Country Link
JP (1) JPS55157040A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5795333A (en) * 1980-10-15 1982-06-14 Verdol Sa Drive restoring mechanism due to pulley
JPS59121554A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Processor backup system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5795333A (en) * 1980-10-15 1982-06-14 Verdol Sa Drive restoring mechanism due to pulley
JPH0231142B2 (en) * 1980-10-15 1990-07-11 Etaburisuman Sutooburi Berudoru
JPS59121554A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Processor backup system
JPH0218504B2 (en) * 1982-12-28 1990-04-25 Fujitsu Ltd

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