JPS5637658A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5637658A
JPS5637658A JP11294079A JP11294079A JPS5637658A JP S5637658 A JPS5637658 A JP S5637658A JP 11294079 A JP11294079 A JP 11294079A JP 11294079 A JP11294079 A JP 11294079A JP S5637658 A JPS5637658 A JP S5637658A
Authority
JP
Japan
Prior art keywords
emitters
base
pads
improper
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11294079A
Other languages
Japanese (ja)
Inventor
Shuroku Sakurada
Isao Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11294079A priority Critical patent/JPS5637658A/en
Publication of JPS5637658A publication Critical patent/JPS5637658A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839—Cathode regions of thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the yield of producing a semiconductor device by independently forming emitters in one pellet becoming a base when forming transistor or gate-turn-off thyristor or the like, executing a characteristic inspection in this state and rejecting an improper emitter through screening. CONSTITUTION:E-shaped emitters 12-15 are independently formed in one pellet 10 becoming a base 11 of a gate-turn-of thyristor or the like. Then, bonding pads 16- 19 are formed at these emitters respectively, and pads 21, 22 are also formed on the base 11. Thereafter, base lead wires 24, 25 are connected to the pads 21, 22 respectively, and the emitters 12-15 are executed with a characteristic inspection in this state. When the emitter 15 is then assumed to be improper, an improper mark is attached to the pad 19 corresponding thereto, and emitter lead wires 26- 28 are connected only to the pads 16-18 except it.
JP11294079A 1979-09-05 1979-09-05 Semiconductor device Pending JPS5637658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11294079A JPS5637658A (en) 1979-09-05 1979-09-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11294079A JPS5637658A (en) 1979-09-05 1979-09-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5637658A true JPS5637658A (en) 1981-04-11

Family

ID=14599299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11294079A Pending JPS5637658A (en) 1979-09-05 1979-09-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5637658A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205035A (en) * 1989-02-02 1990-08-14 Nec Yamagata Ltd Semiconductor device
JPH0364928A (en) * 1989-08-02 1991-03-20 Nec Corp Semiconductor device
JP2006210786A (en) * 2005-01-31 2006-08-10 Matsushita Electric Ind Co Ltd Transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205035A (en) * 1989-02-02 1990-08-14 Nec Yamagata Ltd Semiconductor device
JPH0364928A (en) * 1989-08-02 1991-03-20 Nec Corp Semiconductor device
JP2006210786A (en) * 2005-01-31 2006-08-10 Matsushita Electric Ind Co Ltd Transistor

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