JPS5634198A - Releaving method of deficient bit of semiconductor memory - Google Patents

Releaving method of deficient bit of semiconductor memory

Info

Publication number
JPS5634198A
JPS5634198A JP10879779A JP10879779A JPS5634198A JP S5634198 A JPS5634198 A JP S5634198A JP 10879779 A JP10879779 A JP 10879779A JP 10879779 A JP10879779 A JP 10879779A JP S5634198 A JPS5634198 A JP S5634198A
Authority
JP
Japan
Prior art keywords
deficient
line
residual
lines
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10879779A
Other languages
English (en)
Inventor
Junzo Yamada
Koji Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10879779A priority Critical patent/JPS5634198A/ja
Publication of JPS5634198A publication Critical patent/JPS5634198A/ja
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP10879779A 1979-08-27 1979-08-27 Releaving method of deficient bit of semiconductor memory Pending JPS5634198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10879779A JPS5634198A (en) 1979-08-27 1979-08-27 Releaving method of deficient bit of semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10879779A JPS5634198A (en) 1979-08-27 1979-08-27 Releaving method of deficient bit of semiconductor memory

Publications (1)

Publication Number Publication Date
JPS5634198A true JPS5634198A (en) 1981-04-06

Family

ID=14493719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10879779A Pending JPS5634198A (en) 1979-08-27 1979-08-27 Releaving method of deficient bit of semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5634198A (ja)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460997A (en) * 1981-07-15 1984-07-17 Pacific Western Systems Inc. Memory tester having memory repair analysis capability
JPS59180898A (ja) * 1983-03-31 1984-10-15 Hitachi Ltd 不良ビット救済方法
JPS59207496A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd 半導体メモリ不良ビット救済解析装置
JPS59207497A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd メモリ不良ビット救済解析方法
JPS60209999A (ja) * 1984-04-02 1985-10-22 Hitachi Ltd Ｉｃメモリの救済方式
JPS62214598A (ja) * 1986-03-10 1987-09-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 二次元メモリ・アレイにおける冗長ラインの割当て方法
JPS63185000A (ja) * 1987-01-27 1988-07-30 Hitachi Electronics Eng Co Ltd メモリｉｃ検査装置
JPS63202000A (ja) * 1987-02-13 1988-08-22 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン アドレス・ライン・テスト方法
JPS63239696A (ja) * 1987-03-27 1988-10-05 Toshiba Corp 冗長回路付メモリの試験装置
JPH04132095A (ja) * 1990-09-20 1992-05-06 Toshiba Corp 冗長回路付メモリｉｃの試験装置
JPH05205497A (ja) * 1991-10-16 1993-08-13 Internatl Business Mach Corp <Ibm> アレイビルトインセルフテスト（ａｂｉｓｔ）システム、半導体チップのビルトインセルフテストシステム、及びメモリアレイのテスト方法

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460997A (en) * 1981-07-15 1984-07-17 Pacific Western Systems Inc. Memory tester having memory repair analysis capability
JPS59180898A (ja) * 1983-03-31 1984-10-15 Hitachi Ltd 不良ビット救済方法
JPH0241118B2 (ja) * 1983-03-31 1990-09-14 Hitachi Ltd
JPS59207497A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd メモリ不良ビット救済解析方法
JPS59207496A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd 半導体メモリ不良ビット救済解析装置
JPH0241119B2 (ja) * 1983-05-11 1990-09-14 Hitachi Ltd
JPH03720B2 (ja) * 1983-05-11 1991-01-08 Hitachi Ltd
JPS60209999A (ja) * 1984-04-02 1985-10-22 Hitachi Ltd Ｉｃメモリの救済方式
JPS62214598A (ja) * 1986-03-10 1987-09-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 二次元メモリ・アレイにおける冗長ラインの割当て方法
JPH0529998B2 (ja) * 1986-03-10 1993-05-06 Intaanashonaru Bijinesu Mashiinzu Corp
JPS63185000A (ja) * 1987-01-27 1988-07-30 Hitachi Electronics Eng Co Ltd メモリｉｃ検査装置
JPS63202000A (ja) * 1987-02-13 1988-08-22 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン アドレス・ライン・テスト方法
JPS63239696A (ja) * 1987-03-27 1988-10-05 Toshiba Corp 冗長回路付メモリの試験装置
JPH04132095A (ja) * 1990-09-20 1992-05-06 Toshiba Corp 冗長回路付メモリｉｃの試験装置
JPH05205497A (ja) * 1991-10-16 1993-08-13 Internatl Business Mach Corp <Ibm> アレイビルトインセルフテスト（ａｂｉｓｔ）システム、半導体チップのビルトインセルフテストシステム、及びメモリアレイのテスト方法

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