JPS5632831A - Clock driving type logic circuit - Google Patents
Clock driving type logic circuitInfo
- Publication number
- JPS5632831A JPS5632831A JP10836779A JP10836779A JPS5632831A JP S5632831 A JPS5632831 A JP S5632831A JP 10836779 A JP10836779 A JP 10836779A JP 10836779 A JP10836779 A JP 10836779A JP S5632831 A JPS5632831 A JP S5632831A
- Authority
- JP
- Japan
- Prior art keywords
- logic
- gate
- output
- clock pulse
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To make it possible to transfer the output of the 1st logic element to the 2nd logic element without delay, by interposing a ratio type logic element between the 1st and 2nd ratioless logic elements driven by a clock pulse. CONSTITUTION:Between NOR gate 19 and NAND gate 21 driven by clock pulse phi1, ratio type inverter 20 is connected which is not driven by the clock pulse. To one input terminal of NOR gate 19, input signal (d) of logic [1] is supplied and to the other input terminal, input signal (e) of logic [0] is supplied, so that an output signal of logic [0] will be led out of NOR gate 19 at the rise of clock pulse phi1. This output is inverted by inverter 20 without phase delay to obtain an output signal of logic [1]. Consequently, the output signals with no delay between the output of NOR gate 19 and that of NAND gate 21 can be sent out.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10836779A JPS5632831A (en) | 1979-08-24 | 1979-08-24 | Clock driving type logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10836779A JPS5632831A (en) | 1979-08-24 | 1979-08-24 | Clock driving type logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5632831A true JPS5632831A (en) | 1981-04-02 |
Family
ID=14482958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10836779A Pending JPS5632831A (en) | 1979-08-24 | 1979-08-24 | Clock driving type logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5632831A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5290258A (en) * | 1976-01-23 | 1977-07-29 | Mitsubishi Electric Corp | Logic circuit |
JPS5489558A (en) * | 1977-12-14 | 1979-07-16 | Western Electric Co | Multistage logic circuit |
-
1979
- 1979-08-24 JP JP10836779A patent/JPS5632831A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5290258A (en) * | 1976-01-23 | 1977-07-29 | Mitsubishi Electric Corp | Logic circuit |
JPS5489558A (en) * | 1977-12-14 | 1979-07-16 | Western Electric Co | Multistage logic circuit |
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