JPS5632729A - Etching method - Google Patents

Etching method

Info

Publication number
JPS5632729A
JPS5632729A JP10786079A JP10786079A JPS5632729A JP S5632729 A JPS5632729 A JP S5632729A JP 10786079 A JP10786079 A JP 10786079A JP 10786079 A JP10786079 A JP 10786079A JP S5632729 A JPS5632729 A JP S5632729A
Authority
JP
Japan
Prior art keywords
polyimide
film
masks
etching
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10786079A
Other languages
Japanese (ja)
Inventor
Tatsuhiko Niina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10786079A priority Critical patent/JPS5632729A/en
Publication of JPS5632729A publication Critical patent/JPS5632729A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PURPOSE:To obtain a mask having a sufficient thickness and bonding strength by depositing polyimide via a coupling agent on an Si compound film which is contacted with a III-V group compound semiconductor, thereby forming an etching protecting film. CONSTITUTION:CVD SiO2 14, aminosilane 15, and polyimide 16 are overlayed on the surface of a GaP substrate on which a PN junction and a gold electode are provided. When the polyimide liquid is heat-treated and cured, SiO2 and polyimide are strongly stuck together by the polymerization action of aminosiane. Then, a resistmask is applied, and the layers 16 and 15 are etched by hydrazine. The layer 14 is etched by HF, and a hole 17 is perforated. Then, with the SiO2 film 14 and the polyimide film 16 being the masks, the etching is performed with aqua regis, and a groove 18 is provided. At this time, an electrode 13 is protected by fixing the bottom surface of the wafer to an appropriate base plate. In this constitution, since the thickness of the etching masks is sufficiently large, and masks are strongly contacted with the wafer the electrode 12 is perfectly protected.
JP10786079A 1979-08-23 1979-08-23 Etching method Pending JPS5632729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10786079A JPS5632729A (en) 1979-08-23 1979-08-23 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10786079A JPS5632729A (en) 1979-08-23 1979-08-23 Etching method

Publications (1)

Publication Number Publication Date
JPS5632729A true JPS5632729A (en) 1981-04-02

Family

ID=14469897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10786079A Pending JPS5632729A (en) 1979-08-23 1979-08-23 Etching method

Country Status (1)

Country Link
JP (1) JPS5632729A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5230167A (en) * 1975-09-03 1977-03-07 Hitachi Ltd Method for production of semiconductor device
JPS53107274A (en) * 1977-03-02 1978-09-19 Hitachi Ltd Forming method of patterns

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5230167A (en) * 1975-09-03 1977-03-07 Hitachi Ltd Method for production of semiconductor device
JPS53107274A (en) * 1977-03-02 1978-09-19 Hitachi Ltd Forming method of patterns

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