GB1293807A - Semiconductor wafers sub-dividable into pellets and methods of fabricating same - Google Patents

Semiconductor wafers sub-dividable into pellets and methods of fabricating same

Info

Publication number
GB1293807A
GB1293807A GB5744269A GB5744269A GB1293807A GB 1293807 A GB1293807 A GB 1293807A GB 5744269 A GB5744269 A GB 5744269A GB 5744269 A GB5744269 A GB 5744269A GB 1293807 A GB1293807 A GB 1293807A
Authority
GB
United Kingdom
Prior art keywords
grooves
oxide
glass
wafer
division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5744269A
Inventor
Gary S Sheldon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of GB1293807A publication Critical patent/GB1293807A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Dicing (AREA)
  • Formation Of Insulating Films (AREA)
  • Thyristors (AREA)

Abstract

1293807 Semi-conductor device GENERAL ELECTRIC CO 24 Nov 1969 [9 Dec 1968] 57442/69 Heading H1K [Also in Division C7] A junction containing semi-conductor wafer is passivated by covering at least one of the surfaces with insulation to leave certain areas exposed, removing material from these areas to below a junction and electrophoretically depositing a passivating material, e.g. glass or plastics, into the grooves so formed. Typically a silicon wafer with several junctions is surface oxidized in steam, has registering grids cut in the oxide on opposite faces by etching through a photo-resist or wax mask and is then treated in an etchant to form intersecting sets of grooves extending through the junctions nearest to each face. The oxide overhanging the grooves may be left or removed by brushing or immersion in an ultrasonically agitated inert fluid. An oxide layer up to 500 Š thick is next formed on the groove walls preferably by treatment with an oxidizing agent such as hydrogen peroxide of strong nitric acid. This treatment improves adhesion of the glass electrophoretically deposited in the next step, in which a number or wafers are treated sequentially in an apparatus, operation of which is described in detail. If the oxide overhang was removed the glass increases in thickness towards the base of the grooves, while if it is left on the reverse is true. After firing to coalesce the glass particles electrodes are provided, either before or after sub-division, e.g. by scribing along the grooves, in apertures grit blasted or etched through the oxide. In the completed controlled rectifier shown in Fig. 8 in which the electrodes consist of superposed vapour deposited layers of chromium, nickel and silver, one electrode is soldered to heat sink 804. The wafer is then coated with resilient silicone rubber 814 and a rigid silicone casing 812 injection moulded around it. The invention is also described applied in PN, PIN, PNP and NPN structures with the grooves sometimes limited to one face.
GB5744269A 1968-12-09 1969-11-24 Semiconductor wafers sub-dividable into pellets and methods of fabricating same Expired GB1293807A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US78209368A 1968-12-09 1968-12-09

Publications (1)

Publication Number Publication Date
GB1293807A true GB1293807A (en) 1972-10-25

Family

ID=25124923

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5744269A Expired GB1293807A (en) 1968-12-09 1969-11-24 Semiconductor wafers sub-dividable into pellets and methods of fabricating same

Country Status (6)

Country Link
BE (1) BE742700A (en)
DE (1) DE1961230C3 (en)
FR (1) FR2025718B1 (en)
GB (1) GB1293807A (en)
IE (1) IE33405B1 (en)
SE (1) SE367281B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2600321A1 (en) * 1975-01-16 1976-07-22 Philips Nv METHOD FOR PRODUCING SEMICONDUCTOR ARRANGEMENTS IN WHICH A GLASS COATING IS APPLIED TO A SEMICONDUCTOR DISC, AND SEMICONDUCTOR ARRANGEMENTS PRODUCED BY THIS PROCESS
DE3143216A1 (en) * 1980-10-31 1982-06-03 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Semiconductor device and process for producing a semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3247938A1 (en) * 1982-12-24 1984-07-05 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Semiconductor device having high reverse-voltage handling capacity
US4822757A (en) * 1987-11-10 1989-04-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE666930C (en) * 1936-09-26 1938-11-01 Philips Patentverwaltung Method for producing a top layer
FR1347043A (en) * 1961-09-29 1963-12-27 Ibm Coated articles and processes for producing their protective coatings
DE1439460A1 (en) * 1964-10-19 1968-12-12 Siemens Ag Electrical component, in particular semiconductor component, with a cover made of insulating material
US3505571A (en) * 1965-09-30 1970-04-07 Gen Electric Glass covered semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2600321A1 (en) * 1975-01-16 1976-07-22 Philips Nv METHOD FOR PRODUCING SEMICONDUCTOR ARRANGEMENTS IN WHICH A GLASS COATING IS APPLIED TO A SEMICONDUCTOR DISC, AND SEMICONDUCTOR ARRANGEMENTS PRODUCED BY THIS PROCESS
DE3143216A1 (en) * 1980-10-31 1982-06-03 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Semiconductor device and process for producing a semiconductor device

Also Published As

Publication number Publication date
DE1961230A1 (en) 1970-06-25
IE33405B1 (en) 1974-06-12
FR2025718B1 (en) 1974-05-24
FR2025718A1 (en) 1970-09-11
DE1961230B2 (en) 1974-02-21
BE742700A (en) 1970-06-05
SE367281B (en) 1974-05-20
DE1961230C3 (en) 1974-09-26
IE33405L (en) 1970-06-09

Similar Documents

Publication Publication Date Title
US3122817A (en) Fabrication of semiconductor devices
US4038110A (en) Planarization of integrated circuit surfaces through selective photoresist masking
US3184823A (en) Method of making silicon transistors
US3442701A (en) Method of fabricating semiconductor contacts
US3673016A (en) Method of dividing a semiconductor wafer
US3394037A (en) Method of making a semiconductor device by masking and diffusion
US3913217A (en) Method of producing a semiconductor device
US3454835A (en) Multiple semiconductor device
US3456168A (en) Structure and method for production of narrow doped region semiconductor devices
US3419956A (en) Technique for obtaining isolated integrated circuits
US3595719A (en) Method of bonding an insulator member to a passivating layer covering a surface of a semiconductor device
US3388048A (en) Fabrication of beam lead semiconductor devices
GB1293807A (en) Semiconductor wafers sub-dividable into pellets and methods of fabricating same
US3303071A (en) Fabrication of a semiconductive device with closely spaced electrodes
US3471922A (en) Monolithic integrated circuitry with dielectric isolated functional regions
US3988765A (en) Multiple mesa semiconductor structure
CA1038969A (en) Edge contouring of semiconductor wafers
US3597287A (en) Low capacitance field effect transistor
US4067100A (en) Method of making a semiconductor device
US3187403A (en) Method of making semiconductor circuit elements
US3457631A (en) Method of making a high frequency transistor structure
US3294600A (en) Method of manufacture of semiconductor elements
JPS5745947A (en) Mos type semiconductor integrated circuit
EP0463669B1 (en) A method of manufacturing a semiconductor device
US3658610A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PS Patent sealed
746 Register noted 'licences of right' (sect. 46/1977)
PE20 Patent expired after termination of 20 years