JPS5630741A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5630741A
JPS5630741A JP10641879A JP10641879A JPS5630741A JP S5630741 A JPS5630741 A JP S5630741A JP 10641879 A JP10641879 A JP 10641879A JP 10641879 A JP10641879 A JP 10641879A JP S5630741 A JPS5630741 A JP S5630741A
Authority
JP
Japan
Prior art keywords
film
sio2
layer
wiring
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10641879A
Other languages
Japanese (ja)
Inventor
Takeo Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP10641879A priority Critical patent/JPS5630741A/en
Publication of JPS5630741A publication Critical patent/JPS5630741A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent a disconnection by a method wherein the second layer wiring is overlapped on the first layer of MoS2 through the two layers of Si3N4 and CVD SiO2 in a multilayer wiring. CONSTITUTION:The MoSi2 wiring 1 is formed on an SiO2 film 4 and the two layers of Si3N4 10, CVD SiO2 2 are overlapped. When a resist mask 3 is formed, the SiO2 film 2 is etching eliminated by NH4F+HF, the Si3N4 film 10 prevents the over etching, and then when the Si3N4 film 10 is etched by hot phospheric acid, the SiO2 film 4 under the MoSi film 1 is not etched. In the following, the second layer of polycrystalline Si wiring 11 is made. According to this constitution, since the over etching is not produced on the SiO2 film 4 under the layer of MoSi2 film, consequently the disconnection is not produced on the second layer wiring 11, the reaction with MoSi2 and the deterioration by which O2 is penetrated into a space formed by the over etching at the time of a high temperature processing can be prevented as well.
JP10641879A 1979-08-21 1979-08-21 Semiconductor device Pending JPS5630741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10641879A JPS5630741A (en) 1979-08-21 1979-08-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10641879A JPS5630741A (en) 1979-08-21 1979-08-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5630741A true JPS5630741A (en) 1981-03-27

Family

ID=14433112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10641879A Pending JPS5630741A (en) 1979-08-21 1979-08-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5630741A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066467A (en) * 1983-09-21 1985-04-16 Seiko Epson Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066467A (en) * 1983-09-21 1985-04-16 Seiko Epson Corp Semiconductor device

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