JPS5622974A - Test method for integrated circuit - Google Patents
Test method for integrated circuitInfo
- Publication number
- JPS5622974A JPS5622974A JP9895879A JP9895879A JPS5622974A JP S5622974 A JPS5622974 A JP S5622974A JP 9895879 A JP9895879 A JP 9895879A JP 9895879 A JP9895879 A JP 9895879A JP S5622974 A JPS5622974 A JP S5622974A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- value
- dut7
- generator
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To realize an automatic measurement for the integrated circuit having the hysteresis property, by applying the inclined voltage which increases and decreases by the time to the circuit and then obtaining the property via the arithmetic circuit and with the value by which the output voltage crosses the prescribed voltage each.
CONSTITUTION: Voltage generator 5 applies the step voltage to the positive direction from initial value voltage VP set previously at voltage setting part 6 and then applies successively to the input of device DUT7 to be measured. The output of DUT7 is compared with prescribed value V0 through comparator 8, and voltage value V11 of generator 5 and when crossing value V0 is stored in the 1st memory circuit 9. Then the step polarity is turned negative to be applied successively to the input of DUT7. And in the same way, voltage value V12 of generator 5 and when crossing value V0 is stored in the 2nd memory circuit 10. After this, the value is measured at measuring part 12 for V11 and V12 each, and at the same time the difference (V11-V12) is obtained via arithmetic part 11. In such way, an automatic measurement becomes possible.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9895879A JPS5622974A (en) | 1979-08-02 | 1979-08-02 | Test method for integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9895879A JPS5622974A (en) | 1979-08-02 | 1979-08-02 | Test method for integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5622974A true JPS5622974A (en) | 1981-03-04 |
Family
ID=14233582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9895879A Pending JPS5622974A (en) | 1979-08-02 | 1979-08-02 | Test method for integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5622974A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7035749B2 (en) | 2001-11-26 | 2006-04-25 | Koninklijke Philips Electronics, N.V. | Test machine for testing an integrated circuit with a comparator |
-
1979
- 1979-08-02 JP JP9895879A patent/JPS5622974A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7035749B2 (en) | 2001-11-26 | 2006-04-25 | Koninklijke Philips Electronics, N.V. | Test machine for testing an integrated circuit with a comparator |
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