JPS5621375A - Semiconductor nonvolatile memory device - Google Patents

Semiconductor nonvolatile memory device

Info

Publication number
JPS5621375A
JPS5621375A JP9642179A JP9642179A JPS5621375A JP S5621375 A JPS5621375 A JP S5621375A JP 9642179 A JP9642179 A JP 9642179A JP 9642179 A JP9642179 A JP 9642179A JP S5621375 A JPS5621375 A JP S5621375A
Authority
JP
Japan
Prior art keywords
type
region
film
substrate
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9642179A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6335111B2 (enrdf_load_html_response
Inventor
Shinpei Tsuchiya
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9642179A priority Critical patent/JPS5621375A/ja
Priority to EP80302039A priority patent/EP0021777B1/en
Priority to DE8080302039T priority patent/DE3065360D1/de
Priority to CA000354232A priority patent/CA1139880A/en
Publication of JPS5621375A publication Critical patent/JPS5621375A/ja
Priority to US06/526,219 priority patent/US4491859A/en
Publication of JPS6335111B2 publication Critical patent/JPS6335111B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/686—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP9642179A 1979-06-18 1979-07-28 Semiconductor nonvolatile memory device Granted JPS5621375A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP9642179A JPS5621375A (en) 1979-07-28 1979-07-28 Semiconductor nonvolatile memory device
EP80302039A EP0021777B1 (en) 1979-06-18 1980-06-17 Semiconductor non-volatile memory device
DE8080302039T DE3065360D1 (en) 1979-06-18 1980-06-17 Semiconductor non-volatile memory device
CA000354232A CA1139880A (en) 1979-06-18 1980-06-18 Semiconductor non-volatile memory device
US06/526,219 US4491859A (en) 1979-06-18 1983-08-25 Semiconductor non-volatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9642179A JPS5621375A (en) 1979-07-28 1979-07-28 Semiconductor nonvolatile memory device

Publications (2)

Publication Number Publication Date
JPS5621375A true JPS5621375A (en) 1981-02-27
JPS6335111B2 JPS6335111B2 (enrdf_load_html_response) 1988-07-13

Family

ID=14164509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9642179A Granted JPS5621375A (en) 1979-06-18 1979-07-28 Semiconductor nonvolatile memory device

Country Status (1)

Country Link
JP (1) JPS5621375A (enrdf_load_html_response)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260565A (ja) * 1988-08-26 1990-03-01 Kikkoman Corp 魚介類又は畜肉類エキスフレーバーの安定化法
EP1178540A1 (en) * 2000-07-31 2002-02-06 STMicroelectronics S.r.l. Nonvolatile memory cell with high programming efficiency
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49118376A (enrdf_load_html_response) * 1973-03-12 1974-11-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49118376A (enrdf_load_html_response) * 1973-03-12 1974-11-12

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260565A (ja) * 1988-08-26 1990-03-01 Kikkoman Corp 魚介類又は畜肉類エキスフレーバーの安定化法
EP1178540A1 (en) * 2000-07-31 2002-02-06 STMicroelectronics S.r.l. Nonvolatile memory cell with high programming efficiency
US6734490B2 (en) 2000-07-31 2004-05-11 Stmicroelectronics S.R.L. Nonvolatile memory cell with high programming efficiency
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS6335111B2 (enrdf_load_html_response) 1988-07-13

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