JPS5619574A - Purge control system in conversion index buffer set mechanism - Google Patents

Abstract

PURPOSE: To perform the purge processing efficiently without stopping the processing at the generation of parity error, by purging the entry generating the parity error, in purging the content of the conversion idex buffer mechanism (TLB).

CONSTITUTION: With the coincidence signal through the OR circuit 8 of the comparison circuit 3 with the coincidence of the real address set to the address register 4 and the real address read out from the TLB1 of the entry designated at the purge counter 5, the write-in instruction is made with the output of the AND circuit 9 at high level in synchronizing with the clock and the purge data is written in the designated entry of the counter 5. The readout entry of the TLB1 is checked with the parity check 7, high level signal output by the check 7 is input to the circuit 9 at the generation of error, allowing to write in the purge data also to the error generating entry. The purge processing can efficiently be made without stopping the processing by interruption. Further, the generation of parity error is written in the log register 10 for the use of maintenance of TLB.

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