JPS5619574A - Purge control system in conversion index buffer set mechanism - Google Patents

Purge control system in conversion index buffer set mechanism

Info

Publication number
JPS5619574A
JPS5619574A JP9436279A JP9436279A JPS5619574A JP S5619574 A JPS5619574 A JP S5619574A JP 9436279 A JP9436279 A JP 9436279A JP 9436279 A JP9436279 A JP 9436279A JP S5619574 A JPS5619574 A JP S5619574A
Authority
JP
Japan
Prior art keywords
entry
purge
circuit
processing
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9436279A
Other languages
Japanese (ja)
Inventor
Eizo Fujisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9436279A priority Critical patent/JPS5619574A/en
Publication of JPS5619574A publication Critical patent/JPS5619574A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To perform the purge processing efficiently without stopping the processing at the generation of parity error, by purging the entry generating the parity error, in purging the content of the conversion idex buffer mechanism (TLB).
CONSTITUTION: With the coincidence signal through the OR circuit 8 of the comparison circuit 3 with the coincidence of the real address set to the address register 4 and the real address read out from the TLB1 of the entry designated at the purge counter 5, the write-in instruction is made with the output of the AND circuit 9 at high level in synchronizing with the clock and the purge data is written in the designated entry of the counter 5. The readout entry of the TLB1 is checked with the parity check 7, high level signal output by the check 7 is input to the circuit 9 at the generation of error, allowing to write in the purge data also to the error generating entry. The purge processing can efficiently be made without stopping the processing by interruption. Further, the generation of parity error is written in the log register 10 for the use of maintenance of TLB.
COPYRIGHT: (C)1981,JPO&Japio
JP9436279A 1979-07-25 1979-07-25 Purge control system in conversion index buffer set mechanism Pending JPS5619574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9436279A JPS5619574A (en) 1979-07-25 1979-07-25 Purge control system in conversion index buffer set mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9436279A JPS5619574A (en) 1979-07-25 1979-07-25 Purge control system in conversion index buffer set mechanism

Publications (1)

Publication Number Publication Date
JPS5619574A true JPS5619574A (en) 1981-02-24

Family

ID=14108184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9436279A Pending JPS5619574A (en) 1979-07-25 1979-07-25 Purge control system in conversion index buffer set mechanism

Country Status (1)

Country Link
JP (1) JPS5619574A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5164336A (en) * 1974-12-02 1976-06-03 Fujitsu Ltd
JPS5387631A (en) * 1977-01-12 1978-08-02 Hitachi Ltd Information processing unit
JPS5387632A (en) * 1977-01-12 1978-08-02 Hitachi Ltd Information processing unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5164336A (en) * 1974-12-02 1976-06-03 Fujitsu Ltd
JPS5387631A (en) * 1977-01-12 1978-08-02 Hitachi Ltd Information processing unit
JPS5387632A (en) * 1977-01-12 1978-08-02 Hitachi Ltd Information processing unit

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