JPS56168253A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS56168253A
JPS56168253A JP7207180A JP7207180A JPS56168253A JP S56168253 A JPS56168253 A JP S56168253A JP 7207180 A JP7207180 A JP 7207180A JP 7207180 A JP7207180 A JP 7207180A JP S56168253 A JPS56168253 A JP S56168253A
Authority
JP
Japan
Prior art keywords
data
data transfer
control device
devices
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7207180A
Other languages
Japanese (ja)
Other versions
JPS6019820B2 (en
Inventor
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7207180A priority Critical patent/JPS6019820B2/en
Publication of JPS56168253A publication Critical patent/JPS56168253A/en
Publication of JPS6019820B2 publication Critical patent/JPS6019820B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To easily perform addition and separation of control information by providing address registers separating specific parts within a data transfer control device for the data transferred between upper devices and lower devices within the control device. CONSTITUTION:In the data buffer of a data transfer control device, an address register 2 is used for data transfer to and from a main storage device which is an upper device, an address register 4 is used for transfer with lower devices, for example, a magnetic disc device, and an address register 3 for access of the bufer from the control device and for the access from lower devices. In the data transfer from the upper devices to the lower devices, first data are successively stored in the storage positions of a buffer memory 1 designated by the address register 2. The data are then fetched from the positions designated by the register 4 by the request from the lower devices. If the control information that the control device requires is included in said data, the address indicating said byte position is set in the register 3 and is fetched from the buffer area.
JP7207180A 1980-05-29 1980-05-29 data transfer control device Expired JPS6019820B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7207180A JPS6019820B2 (en) 1980-05-29 1980-05-29 data transfer control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7207180A JPS6019820B2 (en) 1980-05-29 1980-05-29 data transfer control device

Publications (2)

Publication Number Publication Date
JPS56168253A true JPS56168253A (en) 1981-12-24
JPS6019820B2 JPS6019820B2 (en) 1985-05-18

Family

ID=13478798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7207180A Expired JPS6019820B2 (en) 1980-05-29 1980-05-29 data transfer control device

Country Status (1)

Country Link
JP (1) JPS6019820B2 (en)

Also Published As

Publication number Publication date
JPS6019820B2 (en) 1985-05-18

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