JPS5797159A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS5797159A
JPS5797159A JP55173554A JP17355480A JPS5797159A JP S5797159 A JPS5797159 A JP S5797159A JP 55173554 A JP55173554 A JP 55173554A JP 17355480 A JP17355480 A JP 17355480A JP S5797159 A JPS5797159 A JP S5797159A
Authority
JP
Japan
Prior art keywords
memory
buffer
status
data
disk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55173554A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55173554A priority Critical patent/JPS5797159A/en
Publication of JPS5797159A publication Critical patent/JPS5797159A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To shorten an access time for disk memory, and also to make a device have interchangeability with conventional system, by placing a buffer memory between a main memory and a disk memory. CONSTITUTION:A buffer memory 4 placed between a main memory 2 and a disk memory 5 is constituted of a buffer 13, a status display part 12 for holding a read data status to memory 4 in accordance with each location of said buffer 13, and a control flag 11 consisting of mark information showing whether contents of the buffer 13 are effective or not, and address information of the memory 5. A CPU1 checks whether a disk address data is present in the memory 4 or not, in accordance with the flag 11, and when it is present, a data and status of the location concerned of the buffer 13 are transferred to the main memory 2, and if it is not present, the memory 5 is accessed, a data and status of each sector are stored in the memory 4, also, contents of the flag 11 are updated, and the data and status of the location concerned of the memory 4 are transferred to the main memory 12.
JP55173554A 1980-12-09 1980-12-09 Data processing device Pending JPS5797159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173554A JPS5797159A (en) 1980-12-09 1980-12-09 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173554A JPS5797159A (en) 1980-12-09 1980-12-09 Data processing device

Publications (1)

Publication Number Publication Date
JPS5797159A true JPS5797159A (en) 1982-06-16

Family

ID=15962688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173554A Pending JPS5797159A (en) 1980-12-09 1980-12-09 Data processing device

Country Status (1)

Country Link
JP (1) JPS5797159A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5054249A (en) * 1973-09-11 1975-05-13
JPS5133608A (en) * 1974-09-17 1976-03-22 Hitachi Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5054249A (en) * 1973-09-11 1975-05-13
JPS5133608A (en) * 1974-09-17 1976-03-22 Hitachi Ltd

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