JPS6019820B2 - data transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control device that can easily add and separate control information to and from data transferred between a higher-level device and a lower-level device within the data transfer control device. It is something.

As a subsidiary, it has a data buffer in the data transfer control device,
When controlling the transfer of data between a higher-level device and a lower-level device, the control device identifies identification information (m), physical address (PA), etc. for the data transferred from the higher-level device.
), flags (F), etc. are added to the data to be transferred to the lower-level device, and the control information is removed from the data transferred from the lower-level device and the data is transferred to the higher-level device.

There are two conventional methods for handling control equipment notifications: In the first method, in addition to the normal data buffer for handling data transferred between the higher-level device and the lower-level device,
A dedicated buffer is provided for the control device to handle control information in the transferred data.

The second method uses memory as a single buffer, has address registers for transfers with upper and lower devices, and controls the initial values of these registers so that the control device can control the control information in the transferred data. It is made so that it can be handled. However, the former has the disadvantage of complicating the configuration related to the dedicated buffer, and the latter has the disadvantage that the transfer unit with the higher-level device is logical data, especially in the case of energy disk devices, whereas the lower-level device has multiple physical Since the physical data is often separated into data, there is a drawback that control of the data buffer becomes extremely complicated when the control device needs to add and separate control information to and from this physical data. An object of the present invention is to prevent the addition of control information to data transferred between a higher-level device and a lower-level device within a data transfer control device.
An object of the present invention is to provide a data transfer control device that can easily perform separation.

In order to achieve the above object, the data transfer control device of the present invention includes a data buffer memory for data transfer between a higher-level device and a lower-level device, and a data buffer memory for transferring data between the higher-level device or the lower-level device. A data transfer control device comprising first and second address registers for accessing the data buffer memory for storage and transfer, the data buffer memory comprising first and second areas; The area No. 3 stores data transferred between the upper device and the lower device, and the first and second address registers are configured so that only the first area can be accessed, and the second area stores data transferred between the upper device and the lower device. In order to add the control information generated within the control device to the transfer data and send it out, the control information is stored in advance, and the control information included in the transfer data sent from either the upper or lower device is stored in the upper or lower device. This is for separately storing only the control information that is not transferred to the other side of the data buffer memory, and the control information is stored in the second area of the data buffer memory, and the control information is transferred from the first and second areas. The device is characterized in that it includes a third address register that includes the second area and accesses the first and second areas for sending out data.

The present invention will be described in detail below with reference to examples.

For example, in the case of a energy disk device as the above-mentioned lower-level device, identification data (m), physical address (PA), flag (F),
Necessary data such as data length (DL) is recorded, and these are required as control information within the data transfer control device.

There are two types of control information: one is sent from the host device during write operation, and the other is generated within the control device.
Furthermore, there are some items that do not need to be sent to the higher-level device during a read operation, and some that are also sent to the higher-level device. In the present invention, the data buffer memory is divided into two areas.
As means for accessing the area of the data buffer, a first address register dedicated to the upper device and a second address register dedicated to the lower device side are prepared, and as means for accessing the second area of the data buffer, the control device and the host device , a third address register that can be used by lower-level devices is provided, and the first and second address registers are used for normal data transfer, and the third address register is used for storing and transferring control information. By doing so, the control information can be efficiently handled within the control device. FIG. 1 is an explanatory diagram showing the configuration of an embodiment of a data transfer control device which is a main part of the present invention.

This figure shows the configuration of the data buffer of the data transfer control device, and buffer register 1 is a memory with a capacity of 256 bytes.

Address register 2 is used for data transfer with a host device, such as a main memory, and accesses a 128-byte area of the buffer register. The address register 4 is used for data transfer with lower-order devices, such as energy disk devices, and is accessed correspondingly to the 128-byte memo file in the address register 2 of the buffer register 1. Therefore, in normal data transfer, a 128-byte area of buffer register 1 is used as a data buffer. Address register 3 is the main part of the present invention, and can access the entire 256 bytes of buffer register 1.
Used for buffer access from the control device and access from lower devices. Although the use of the address register 3 can also be made possible from a higher-level device, in this embodiment, in order to simplify understanding, it is assumed that the address register 3 is not used from the higher-level device side. Therefore, when accessing from the lower device side, an instruction is given as to which address register 3 or 4 is to be used. Further, the address registers 2, 3, and 4 are constituted by counters, and are incremented from a preset value at the end of access. In data transfer from a higher-level device to a lower-level device, data sent from the higher-level device via the bus 5 is sequentially stored in the storage location of the buffer memory 1 specified by the address register 2, and data requests from the lower-level device are Accordingly, the data to be transferred is extracted from the storage location specified by the address register 4 via the bus 6 and sent to the lower device.

When these data include control information required by the control device, the control device sets the byte position in the address register 3 and takes it out from the buffer area (0 to 127 bytes). In addition, if data is not sent from the higher-level device but must be sent to the lower-level device, the control device must register the data in the address register in advance.
and set it in a different area (128 bytes or less) from the normal 128 byte area of the buffer memory.
At the data sending timing, the lower device specifies the address register 3 and accesses the buffer area. Data transfer from the lower-level device to the higher-level device uses buses 7 and 8, and is performed in the opposite direction to that described above.

However, for data that does not need to be sent to the upper device among the data from the lower device, address register 3 is used when accessing from the lower device, and by storing it in an area that can be accessed only with the address register,
It can be used later as control information. FIGS. 2 and 3 are explanatory diagrams of an embodiment of the present invention in which a nutrition disk device is used as a lower input/output device.

FIG. 2 shows an example of the state of the buffer memory when the data on the storage disk device medium shown in the upper part of FIG. 3 has been transferred to the buffer memory 1 of FIG. 1 to the host device. Other address registers (MA) 2 (IA) 4,
(CA) 3 has the same function as the same number in FIG. Third
The upper part of the figure is an example of data transferred from the energy disk medium. The illustrated 12 bytes of data (ID to DL) are sent from the disk device to the control device, and the last 8 bytes of data (C to DL) are sent from the disk device to the control device. ) is transferred to the higher-level device.

CA and lAMA at the bottom of FIG. 3 indicate the progress states of the three address registers 3, 4, and 2 in FIG. 2 at each data transfer timing.

That is, when transferring the first 4 bytes, the address register (CA) 3 is used, and control information such as m, PA, F, etc. mentioned above is stored in the address area of 128 to 131 bytes.

This area is normally used as a transfer buffer from 0 to 12.
Even if the data is outside the 7-byte area and is not transferred to the host device, or if the subsequent actual transferred data (in this case 8 bytes) exceeds 12 & 8 bytes, it may be overwritten as the transfer progresses. It cannot be destroyed. Next, after the transfer of 4 bytes is completed, the address register (IA) 4 is switched to be used for access from the lower device side, and data is stored in order from address "0".

The host device side indicates that the data to be transferred has been stored, for example, by using address register (MA) 2 and address register (
IA) Known from the difference of 4, address register (MA) 2
to start the transfer to the higher-level device. Although not shown, the address register to be used upon access from the lower device side can be easily switched by using a counter or a comparison circuit.

In the embodiment, although the use of the third address register from the upper device side is not particularly discussed, it can be easily incorporated using the same method as used from the lower device side.

As described above, according to the present invention, an area other than a data buffer area for accessing data transferred between a higher-level device and a lower-level device within a data transfer control device;
By providing an address register for accessing this, control information can be easily added to and separated from transfer data.

That is, a separate area for control information is provided within a single data buffer memory for complex control, and this area and a normal buffer area are designated by simple logic using address registers 3-5. In this way, it is possible to transfer data between the higher-level device and the lower-level device, and to easily add and separate control information required by the control device to the transferred data.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIG.
FIG. 3 is an explanatory diagram of an embodiment in which the present invention is applied to a nutrition disk control device, and in the figure, 1 is a data buffer memory;
2, 3, and 4 are address registers, and 5, 6, 7, and 8 are data buses. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A data buffer memory for data transfer between a higher-level device and a lower-level device; and a data buffer memory for storing and transferring data transferred between a higher-level device or a lower-level device in the data buffer memory. The data transfer control device includes first and second address registers to be accessed, and the data buffer memory is composed of a first and second area, and the first area is connected to an upper device and a lower device. It stores data transferred between
The first and second address registers are configured so that only the first area can be accessed, and the second area stores control information in advance in order to add control information generated within the control device to transfer data and send it out. , and also separately stores only the control information that is not transferred to the other of the upper or lower devices among the control information included in the transfer data sent from one of the upper or lower devices, and In order to store control information in the second area of the data buffer memory and to transmit control information from the first and second areas, the data buffer memory includes the second area and the first and second areas. A data transfer control device comprising a third address register to be accessed.