JPS61100852A - Data transferring system - Google Patents

Abstract

PURPOSE:To shorten the time for processing by storing data of block unit in a discontinuous address space of a main memory in a direct memory access mode. CONSTITUTION:A processor 5 indicates an address that indicates a discontinuous address space of a main memory 6 and the number of bytes of a block that indicates data length of a arbitrary length to a subprocessor 9 that controls a disk control channel 7. The subprocessor 9 develops the address and the number of bytes in a buffer 10. A DMA controlling section 14 sends a command to the main memory 6, and transfers data of a buffer 15 to the address space of the main memory 6 designated by an address counter 11. When a transfer byte counter 12 becomes zero, and the content of the buffer 10 is out, a count value loading section 13 gives a notice interrupting the subprocessor 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a method for moving data between blocks of data through main memory in direct memory access mode between a high speed channel and another high speed channel. This paper relates to a data transfer method when inputting control information into a file.

In computer systems, data is often transferred in direct memory access mode between input/output devices connected to channels operating at high speed via main memory. For example, when data is transferred between a high-speed channel that controls a magnetic tape device operating in streaming mode (continuous running mode) and a high-speed channel that controls a disk device, the data read from the magnetic tape device is transferred to direct memory. - Depending on the access mode, - it is stored in mutual storage and then written to the disk device.

Further, data read from the disk device is similarly stored in the main memory and then written to the magnetic tape device.

By the way, data management methods are different between magnetic tapes and disks, so control information such as a header may be added to the beginning of a data block, but it is necessary that adding this control information does not increase the burden on the processor. be.

[Conventional technology]

FIG. 3 is a diagram illustrating a conventional data transfer method.

Data read from the disk 2 in the direct memory access mode is successively written into the main memory 1 as blocks fa) and blocks (b). In order to add a control information header to the block of data written in the main memory 1, the processor moves the block on the main memory 1 and adds a header ( a
Add a block (header mountain to the beginning of bl) to l.

The headers (al block (a), header (b), and block (b) to which control information has been added in the main memory 1'' are sequentially transferred to the magnetic tape 3 in direct memory access mode to complete the data transfer.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, direct memory data from disk
Depending on the access mode, the processor moves each block of data stored in main memory in main memory and adds control information, which places a burden on the processor and slows down processing by the time it takes to move the block. There's a problem.

[Means for solving problems]

The above problem is that in a channel that controls an input/output device that sends and receives data, an address indicating a discontinuous address space in main memory and the number of bytes of arbitrary data length to be stored in the address space are stored. a storage means for sequentially transmitting the data, an instruction means for instructing the main memory of the address given from the storage means, and an instruction means for counting the number of bytes of data to be stored at the address designated by the instruction means and receiving the data given from the storage means. a counting means for sending a signal when the number of bytes is reached;
A setting means is provided for reading the next address and number of bytes from the storage means in response to a signal from the counting means and setting them in the instruction means and the counting means, respectively. By storing the information and activating the setting means at the initial
The problem is solved by the data transfer method according to the present invention, which stores data from the input/output device in the main memory using a memory access mode.

[Effect]

That is, when the channel transfers data to the main memory, the data can be transferred to discontinuous address spaces in units of blocks.

〔Example〕

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

The processor 5 instructs the sub-processor 9, which controls the disk control channel 7, an address indicating a discontinuous address space in the main memory 6 and the number of bytes of a block indicating an arbitrary data length.

Sub-processor 9 develops this address and number of bytes into buffer IO. Buffer 10 is a memory configured such that data stored first is read out first.

FIG. 2 is a diagram illustrating the contents developed in the buffer 10.

Following the first address ■, the number of bytes in the block stored in the space at this address ■, then the address ■, an address that is discontinuous with the space, and the number of bytes in the block, and after the above repetition, the last address ■ and the number of bytes■ are expanded.

First, the sub-processor 9 activates the count value loading section 13. The count value loading section 13 loads the address ■ into the address counter 11 and the number of bytes ■ into the transfer byte counter 12 from the buffer 10 .

Here, the subprocessor 9 activates the DMA (direct memory access) control section 14 and controls the disk control section 16 to read data from the disk 8 and store it in the buffer 15.

The DMA IJ control section 14 sends a command to the main memory 6, and transfers the data in the buffer 15 to the address space of the main memory 6 indicated by the address counter 11. The transfer byte counter 12 counts the number of transferred bytes, and when the loaded byte number becomes zero, the count value loading section 13
Start. The count value loading unit 13 loads the address ■ from the buffer 10 into the address counter 11 and the number of bytes ■ into the transfer byte counter 12 .

The DMA control unit 14 then transfers the data in the buffer 15 to the address ■ space of the main memory 6 according to the address ■ indicated by the address counter 11 .

When the number of bytes loaded in the transfer byte counter 12 becomes zero, the count value loading unit 13 is activated.

By repeating the above operations, when the transfer byte counter 12 becomes zero and the contents of the buffer 10 are exhausted, the count value loading unit 13 raises an interrupt to notify the sub-processor 9.

〔Effect of the invention〕

As explained above, the present invention can store blocks of data in the discontinuous address space of the main memory in the direct memory access mode, so the processor is required to add control information to each block. There is no need to move data, and processing time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a diagram illustrating contents developed in a buffer 10, and FIG. 3 is a diagram illustrating a conventional data transfer method. In the figure, 5 is a processor, 6 is a main memory, 7 is a disk control channel, 8 is a disk, 9 is a subprocessor, 10,
15 is a buffer, 11 is an address counter, 12 is a transfer byte counter, 13 is a count value load section, 14 is a DMA IIJ control section, and 16 is a disk control section.

Claims (1)

[Claims] In a channel that controls an input/output device that sends and receives data, a storage device that sends an address indicating a discontinuous address space in main memory and the number of bytes of arbitrary data length to be stored in the address space in the order in which they are stored. and instruction means for instructing the main memory to the address given from the storage means, and counting the number of bytes of data stored at the address indicated by the instruction means, and when the number of bytes given from the storage means is reached. A processor for controlling a channel is provided with a counting means for sending a signal, and a setting means for reading an address and a number of bytes stored in the storage means based on the signal from the counting means and setting them in the instruction means and the counting means, respectively. A data transfer method characterized in that data of the input/output device is stored in a main memory in a direct memory access mode by storing an address and a number of bytes in the storage means and activating the setting means at an initial time. .