JPS60198663A - Control system and circuit for data transfer - Google Patents

Abstract

PURPOSE:To perform simultaneously both editing and transfer of a data frame at a high speed by writing data frames successively to each memory area of divided buffer memory means and then reading both the fixed length data and the unfixed length data of the data frame in a prescribed order. CONSTITUTION:A data transfer control system comprises the 1st and 2nd data processors 4 and 6 and a transfer control circuit 5. The circuit 5 contains a frame buffer 2 which can store four data frames consisting of the fixed length and unfixed length data divided logically. The data frames are successively written to the buffer 2 and at the same time the written fixed and unfixed length data are read out in a prescribed order. These controls are performed by unfixed length bit detecting circuits 7 and 10, an order control circuit 11 and counters 8, 9 and 12-15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control circuit that controls the transfer order of data in a plurality of data frames each consisting of fixed length data and undefined length data.

When transferring a data frame consisting of fixed length data and variable length data added to this fixed length data (hereinafter referred to as undefined length data) between the transmitting side and the receiving side, the transmitting side transfers each data frame. Continuous sequential delivery, while
On the receiving side, fixed length data may be received several data frames in advance and rearranged between fixed length data and undefined length data. Such conventional reordering during data transfer requires a large capacity storage device for editing on the sending or receiving side, and has the disadvantage that editing takes a lot of time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control circuit that eliminates the above-mentioned drawbacks.

The circuit of the present invention is a data transfer control circuit that controls the transfer order of each data of a plurality of data frames each including at least one of fixed-length data and undefined-length data. a buffer storage means capable of storing a predetermined number of the data frames; first and second storage area designating means for specifying the storage area to which the data frame is to be written and a storage position within the storage area; first reading means for reading out the fixed length data stored in the area specified by the first storage area specification means; Further, according to the present invention, the present invention further comprises a second reading means for reading out the indefinite length data stored in the area, and an order control means for controlling the operation order of the first and second reading means. The data transfer control method controls the transfer of each data of a plurality of data frames each containing at least one of fixed-length data and undefined-length data, in which the data is logically divided into a predetermined number of storage areas. Each of the data frames is sequentially written into each storage area of the buffer storage means, and the fixed length data and undefined length data of these written data frames are read out from the buffer storage means in a predetermined order.

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 shows a data file 1 consisting of n data frames D1 to Dn each containing at least one of fixed length data X1 to Xn and undefined length data Y1 to Yn. FIG. 2 shows the contents of 7 frames 7a2 used as a temporary storage circuit for editing data according to the transfer order of data X1 to Xn and Y1 to Yn, and is composed of four sub-buffers 28 to 2d. There is. FIG. 3 shows the edited data file 3.

FIG. 4 is a block diagram showing one embodiment of the present invention. In the figure, the present embodiment is composed of first and second data processing devices 4 and 6, and a transfer control circuit 5, and this transfer control circuit 5 has four storage areas (hereinafter referred to as sub-buffers) 2a. A frame buffer 2 (see Figure 2) that is logically divided into ~2d and can store four data frames consisting of fixed length data and undefined length data, and an undefined length pin (T) that indicates the length of the undefined length data. An undefined length bit detection circuit 7 for detection, a buffer counter 8 for specifying the start address of one of the four sub-buffers 28 to 2d,
An address counter 9 that specifies the address within the sub-buffer specified by the buffer counter 8, an indefinite-length bit detection circuit 10 that detects the indefinite-length bit T in the data frame output from the frame buffer 2, and four sub-buffers. The fixed length data buffer counter 12 and the undefined length data buffer counter 14 designate the start address of one of 28 to 2d, and the fixed length data and undefined length data buffer counters 12 and 14 respectively designate The operating order of the address counters 13 and 15 for fixed-length data and undefined-length data, the buffer counter 12, the address counter 13, the buffer counter 14, and the address counter 15, which specify the address in each sub-buffer, is as follows. and a sequence control circuit 11 that performs control based on.

In FIG. 4, the first data processing device 4 stores the transmitting side data file 1 shown in FIG. The undefined length bit detection circuit 7 first detects the undefined length data Y from the fixed length data X1 of the data frame D1 of the data file 1.
An undefined length bit T indicating the number of bytes of 1 is detected, the number of bytes of the undefined length data Y1 following the fixed length data X1 is decoded, and the number of bytes of the undefined length data Y1 is set in the address counter 9. The contents of the buffer counter 8 are updated every data frame and reset every 4 data frames.

In response to detecting an undefined length bit in data frame D1,
Assume that a value specifying sub-buffer 2a is currently set in counter 8. Data frame D! When the storage of the variable length data Y into the sub-buffer 2a is completed and the indefinite length bit T of the next data frame DI is detected by the detection circuit 7, the number of bytes of the variable length data Y is similarly decoded and stored in the address counter 9. is set. Further, a value specifying the sub-buffer 2b is set in the buffer counter 8.

Similarly, data frames D3 and D4 are stored in sub-buffers 2C and 2d, respectively, and sub-buffer 2
When storage is completed in sub-buffer 2a, the next data frame is stored again from sub-buffer 2a.

In order to input data into the data processing device 6 in the order shown in FIG. 3, the following operations are performed.

■The number of bytes of data Output. The values detected by the undefined length pins outputted at this time are counters 15 and 1, respectively.
Set to 4.

■After the transfer of data X1 is completed, the number of bytes of data
3 and 12, and the control circuit 11 operates the counters 12 and 13 to output data Xs from the 7-frame buffer 2b. Data output at this time Y! The number of bytes and the value specifying the sub-buffer 2b are stored in a temporary storage section provided in the control circuit 11.

■After the transfer of data X2 is completed, the control circuit 11 starts the counter 1
4 and 15 are operated to output data Y1 from the frame buffer 2a.

■After the transfer of data X1 is completed, the number of bytes of data X3 and the value specifying sub-buffer 2C are respectively
3 and 12, and the control circuit 11 operates the counters 12 and 13 to output the data X3 from the sub-buffer 2C, and also outputs the data
Values specifying b are set in counters 15 and 14, respectively. Further, the number of bytes of data Y3 detected by the detection circuit 10 and a value specifying the sub-buffer 2c are stored in the temporary storage section.

Similarly, for the following data transfer, the operations of steps (2) and (2) are alternately repeated to execute the transfer as shown in FIG. 3. In addition, in FIG. 3, data x,,x,,x,,x! , and Y, can be easily performed by appropriately combining steps ① to ②.

As described above, the present invention has the advantage that editing and transfer of multiple data frames including fixed length data and undefined length data can be executed simultaneously and at high speed.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a data file consisting of multiple data frames, Figure 2 is a diagram showing the contents of the editing frame buffer, and Figure 3 is a diagram showing the contents of the editing frame buffer.
The figure shows an edited data file, and FIG. 4 is a block diagram showing an embodiment of the present invention.
2...Frame buffer, 3...Cheetah file on receiving side, 4...First data processing device, 5...Data transfer control circuit, 6・・・・・・
...Second data processing device, 7...Undefined length bit detection circuit, 8...Buffer counter, 9...
... Address counter, 10 ... Undefined length bit detection circuit, 11 ... Sequence control circuit, 12.
... Buffer counter, 13 ... Fixed length data address counter, 14 ... Buffer counter, 15 ... Undefined length data address counter, 16 ... Figure 81 Figure 2 Figure 3

Claims (2)

[Claims] (1) In a data transfer control circuit that controls the transfer order of each data of a plurality of data frames each containing at least one of fixed length data and undefined length data, the data is logically divided into a predetermined number of storage areas. buffer storage means capable of storing a predetermined number of said data frames; writing means for specifying said storage area to which said data frame is to be written and a storage position within said storage area; and said data frame from which said data frame is to be read. first and second storage area specifying means for specifying the storage area; and first storage area specifying means for reading the fixed length data stored in the area specified by the first storage area specifying means. a reading means, a second reading means for reading the indefinite length data stored in the area specified by the second storage area specifying means, and the first and second successive reading means. A data transfer control circuit comprising: order control means for controlling the operation order of the data transfer control circuit. (2) In a data transfer control method that controls the transfer of each data of a plurality of data frames each including at least one of fixed length data and undefined length data,
Each of the data frames is sequentially written into each storage area of a buffer storage means logically divided into a predetermined number of storage areas, and fixed length data and indefinite length data of these written data frames are predetermined. A data transfer control method characterized in that data is read from the buffer storage means in sequence.