JPS56164578A - Manufacture of mos type semiconductor device - Google Patents

Manufacture of mos type semiconductor device

Info

Publication number
JPS56164578A
JPS56164578A JP6637480A JP6637480A JPS56164578A JP S56164578 A JPS56164578 A JP S56164578A JP 6637480 A JP6637480 A JP 6637480A JP 6637480 A JP6637480 A JP 6637480A JP S56164578 A JPS56164578 A JP S56164578A
Authority
JP
Japan
Prior art keywords
layer
openings
polycrystalline
psg
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6637480A
Other languages
Japanese (ja)
Inventor
Shokichi Yoshitome
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP6637480A priority Critical patent/JPS56164578A/en
Publication of JPS56164578A publication Critical patent/JPS56164578A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain the favorable ohmic connection in the MOS tye semiconductor device by a metod wherein openings are formed in a gate oxide film on an Si substrate, while a polycrystalline Si layer being added with P and an Mo layer is laminated thereon, openings are formed therein and are covered with a PSG layer to form diffusion layers, and an opeing is formed in the Mo layer on the connecting hole at the same time with the formation of ooenings for eletrodes and Al wiring is performed. CONSTITUTION:Openings 4 are formed selectively in the gate oxide film 3 on the p type Si substrate 1, and the polycrystalline Si layer 5 doped with P and the Mo layer 6 are laminated thereon. Openings are formed selectively and are covered with a PSG layer 7, and heat-treatment is performed to form N type layers 81, 82. The openings 9 for electrodes are formed in the PSG layer and at the same time the opening 11 is formed in the PSG layer 7 directly over the opening 4. Then the Mo layer 6 at this part is removed by etching to remove the Mo silicide. When an Al wiring 13 is formed on the opening 11 after then, the sides of the polycrystalline Si layer 5 and the Mo layer 6 are connected to enable to obtain the favorable ohmic contact between the gate electrode material and the source or the drain. The ohmic connection between Al and polycrystalline Si or Mo is out of the question.
JP6637480A 1980-05-21 1980-05-21 Manufacture of mos type semiconductor device Pending JPS56164578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6637480A JPS56164578A (en) 1980-05-21 1980-05-21 Manufacture of mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6637480A JPS56164578A (en) 1980-05-21 1980-05-21 Manufacture of mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPS56164578A true JPS56164578A (en) 1981-12-17

Family

ID=13313981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6637480A Pending JPS56164578A (en) 1980-05-21 1980-05-21 Manufacture of mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56164578A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57210668A (en) * 1981-06-19 1982-12-24 Seiko Epson Corp Semiconductor device
JPS6182479A (en) * 1984-09-28 1986-04-26 Sharp Corp Manufacture of semiconductor device
JPS63306658A (en) * 1987-06-08 1988-12-14 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
US5081518A (en) * 1989-05-24 1992-01-14 National Semiconductor Corporation Use of a polysilicon layer for local interconnect in a CMOS or BICMOS technology incorporating sidewall spacers
US5082796A (en) * 1990-07-24 1992-01-21 National Semiconductor Corporation Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers
US5166770A (en) * 1987-04-15 1992-11-24 Texas Instruments Incorporated Silicided structures having openings therein
US5648663A (en) * 1985-08-05 1997-07-15 Canon Kabushiki Kaisha Semiconductor structure having transistor and other elements on a common substrate and process for producing the same
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57210668A (en) * 1981-06-19 1982-12-24 Seiko Epson Corp Semiconductor device
JPS6182479A (en) * 1984-09-28 1986-04-26 Sharp Corp Manufacture of semiconductor device
US5648663A (en) * 1985-08-05 1997-07-15 Canon Kabushiki Kaisha Semiconductor structure having transistor and other elements on a common substrate and process for producing the same
US5686326A (en) * 1985-08-05 1997-11-11 Canon Kabushiki Kaisha Method of making thin film transistor
US5166770A (en) * 1987-04-15 1992-11-24 Texas Instruments Incorporated Silicided structures having openings therein
JPS63306658A (en) * 1987-06-08 1988-12-14 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
US5081518A (en) * 1989-05-24 1992-01-14 National Semiconductor Corporation Use of a polysilicon layer for local interconnect in a CMOS or BICMOS technology incorporating sidewall spacers
US5082796A (en) * 1990-07-24 1992-01-21 National Semiconductor Corporation Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6514811B2 (en) 1993-12-17 2003-02-04 Stmicroelectronics, Inc. Method for memory masking for periphery salicidation of active regions
US6661064B2 (en) 1993-12-17 2003-12-09 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions

Similar Documents

Publication Publication Date Title
JPS56134757A (en) Complementary type mos semiconductor device and its manufacture
JPS56164578A (en) Manufacture of mos type semiconductor device
JPS5562771A (en) Integrated circuit device
JPS5650535A (en) Manufacture of semiconductor device
JPS55157241A (en) Manufacture of semiconductor device
JPS56111264A (en) Manufacture of semiconductor device
JPS56100441A (en) Semiconductor ic device with protection element and manufacture thereof
JPS56125875A (en) Semiconductor integrated circuit device
JPS57149774A (en) Semiconductor device
JPS54154966A (en) Semiconductor electron device
JPS57132352A (en) Complementary type metal oxide semiconductor integrated circuit device
JPS55120170A (en) Mos type semiconductor device
JPS57118662A (en) Manufacture of semiconductor device
JPS56165320A (en) Formation of multilayer electrodes of semiconductor device
JPS57114274A (en) Electrode for semiconductor device and manufacture thereof
JPS567482A (en) Manufacturing of semiconductor device
JPS57153472A (en) Manufacture of semiconductor device
JPS6417475A (en) Manufacture of mos semiconductor device
JPS55125648A (en) Semiconductor integrated circuit
JPS56116668A (en) Semiconductor device and nanufacture thereof
JPS56133869A (en) Mos type semiconductor device and manufacture thereof
JPS5753958A (en) Semiconductor device
JPS57115858A (en) Semiconductor device
JPS57133676A (en) Semiconductor integrated circuit device
JPS56146281A (en) Manufacture of semiconductor integrated circuit