JPS56164576A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS56164576A JPS56164576A JP6858780A JP6858780A JPS56164576A JP S56164576 A JPS56164576 A JP S56164576A JP 6858780 A JP6858780 A JP 6858780A JP 6858780 A JP6858780 A JP 6858780A JP S56164576 A JPS56164576 A JP S56164576A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- emitter
- type
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 238000005468 ion implantation Methods 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To prevent the formation of channel and to obtain a walled emitter construction by self-alignment in the semiconductor device by a method wherein a field insulating film and a base lyer obtained by ion implantation are provided using a double layers mask, and an emitter layer is provided at the part wherein the double layers mask is removed. CONSTITUTION:A film 11 made of SiO2 and Si3N4 and a PSG layer 12 are laminated on an N type Si epitaxial layer 2, and the PSG layer is made to have the smaller size than the film 11. After the field oxide film 3 is formed by oxidation with pressure, the films 11, 12 are removed selectively by sputter etching. The P type base layer 5 is provided by B ion implantation, and a step type junction 16 is formed. Then the film 12 is remoed and is annealed, it is covered with an SiO2 film 17, the film 11 is removed and an opening 18 is formed, and when the N type emitter layer 4 is formed by P ion implantation, one end thereof is made to come in contact with the field oxide film 3. After then an opening is formed in the SiO2 film 17 and electrodes 9B, 9E are adhered as usual. By this constitution, the generation of N type inversion channel can be prevented by making density at the base end part 5a and the interface of field oxide film as 10<17>/cm<2> or lmore, and because the long walled emitter structure can be formed, the withstand voltage between the emitter and the collector can be enhanced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6858780A JPS5941308B2 (en) | 1980-05-23 | 1980-05-23 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6858780A JPS5941308B2 (en) | 1980-05-23 | 1980-05-23 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56164576A true JPS56164576A (en) | 1981-12-17 |
| JPS5941308B2 JPS5941308B2 (en) | 1984-10-05 |
Family
ID=13378067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6858780A Expired JPS5941308B2 (en) | 1980-05-23 | 1980-05-23 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941308B2 (en) |
-
1980
- 1980-05-23 JP JP6858780A patent/JPS5941308B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5941308B2 (en) | 1984-10-05 |
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