JPS55153345A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55153345A
JPS55153345A JP6123479A JP6123479A JPS55153345A JP S55153345 A JPS55153345 A JP S55153345A JP 6123479 A JP6123479 A JP 6123479A JP 6123479 A JP6123479 A JP 6123479A JP S55153345 A JPS55153345 A JP S55153345A
Authority
JP
Japan
Prior art keywords
layer
base
sio2
junction
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6123479A
Other languages
Japanese (ja)
Inventor
Yunosuke Kawabe
Yoshinobu Monma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6123479A priority Critical patent/JPS55153345A/en
Publication of JPS55153345A publication Critical patent/JPS55153345A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To improve dielectric strength by a method wherein on a substrate which has a buried layer an epitaxial layer which has reverse conducting mechanism is laminated and in this layer a base layer which has same conducting mechanism and of which an end is osculated with a dielectric insulation layer is formed and crossing of a base collector junction and an emitter base junction is eliminated. CONSTITUTION:An n<->-epitaxial layer 5 is formed on a p-type substrate 1 which has an n<+>-buried layer, and on an SiO2 film 8 a resist mask 10 is applied, and p-layer 4 is formed by B ion implantation. Next thereto two layered mask of Si3N4 14 and SiO2 is formed, and a concave region 15 is formed by etching away the n<->-layer 5. Next thereto by the concave region 15 filled with SiO2 utilizing high pressure oxidization method, a dielectric isolation layer 2 is formed. Utilizing a conventional method hereafter, after the Si3N4 14 film is removed and the SiO2 film 8 is selectively perfolated for an opening, a resist mask 10' is applied and an n<+>-type emitter 3 and collector 16 are formed by P ion implantation. Next thereto the mask 10' is removed and an electrode is formed. By this constitution a base collector junction 11 and an emitter base junction have not crossing point, and deterioration of dielectric strength or short circuiting can not occur.
JP6123479A 1979-05-18 1979-05-18 Manufacture of semiconductor device Pending JPS55153345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6123479A JPS55153345A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6123479A JPS55153345A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55153345A true JPS55153345A (en) 1980-11-29

Family

ID=13165321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6123479A Pending JPS55153345A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55153345A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929779A (en) * 1972-07-18 1974-03-16
JPS49115688A (en) * 1973-02-21 1974-11-05
JPS5068286A (en) * 1973-10-17 1975-06-07
JPS51146194A (en) * 1975-05-28 1976-12-15 Hitachi Ltd Diode device fabrication method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929779A (en) * 1972-07-18 1974-03-16
JPS49115688A (en) * 1973-02-21 1974-11-05
JPS5068286A (en) * 1973-10-17 1975-06-07
JPS51146194A (en) * 1975-05-28 1976-12-15 Hitachi Ltd Diode device fabrication method

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