JPS561573A - Semiconductor nonvolatile memory - Google Patents

Semiconductor nonvolatile memory

Info

Publication number
JPS561573A
JPS561573A JP7656979A JP7656979A JPS561573A JP S561573 A JPS561573 A JP S561573A JP 7656979 A JP7656979 A JP 7656979A JP 7656979 A JP7656979 A JP 7656979A JP S561573 A JPS561573 A JP S561573A
Authority
JP
Japan
Prior art keywords
regions
region
type
forming
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7656979A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57668B2 (enExample
Inventor
Shinpei Tsuchiya
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7656979A priority Critical patent/JPS561573A/ja
Priority to EP80302039A priority patent/EP0021777B1/en
Priority to DE8080302039T priority patent/DE3065360D1/de
Priority to CA000354232A priority patent/CA1139880A/en
Publication of JPS561573A publication Critical patent/JPS561573A/ja
Publication of JPS57668B2 publication Critical patent/JPS57668B2/ja
Priority to US06/526,219 priority patent/US4491859A/en
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/686—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP7656979A 1979-06-18 1979-06-18 Semiconductor nonvolatile memory Granted JPS561573A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP7656979A JPS561573A (en) 1979-06-18 1979-06-18 Semiconductor nonvolatile memory
EP80302039A EP0021777B1 (en) 1979-06-18 1980-06-17 Semiconductor non-volatile memory device
DE8080302039T DE3065360D1 (en) 1979-06-18 1980-06-17 Semiconductor non-volatile memory device
CA000354232A CA1139880A (en) 1979-06-18 1980-06-18 Semiconductor non-volatile memory device
US06/526,219 US4491859A (en) 1979-06-18 1983-08-25 Semiconductor non-volatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7656979A JPS561573A (en) 1979-06-18 1979-06-18 Semiconductor nonvolatile memory

Publications (2)

Publication Number Publication Date
JPS561573A true JPS561573A (en) 1981-01-09
JPS57668B2 JPS57668B2 (enExample) 1982-01-07

Family

ID=13608856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7656979A Granted JPS561573A (en) 1979-06-18 1979-06-18 Semiconductor nonvolatile memory

Country Status (1)

Country Link
JP (1) JPS561573A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256674A (ja) * 1985-05-09 1986-11-14 Nippon Texas Instr Kk 半導体装置
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6093841A (ja) * 1983-10-27 1985-05-25 Yaesu Musen Co Ltd 受信回路
JPH04103183U (ja) * 1991-12-19 1992-09-04 株式会社精工舎 スイング体
CN109427887B (zh) * 2017-08-29 2022-04-12 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法及半导体器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256674A (ja) * 1985-05-09 1986-11-14 Nippon Texas Instr Kk 半導体装置
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS57668B2 (enExample) 1982-01-07

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