JPS56155454A - Test controller for program - Google Patents

Test controller for program

Info

Publication number
JPS56155454A
JPS56155454A JP5905380A JP5905380A JPS56155454A JP S56155454 A JPS56155454 A JP S56155454A JP 5905380 A JP5905380 A JP 5905380A JP 5905380 A JP5905380 A JP 5905380A JP S56155454 A JPS56155454 A JP S56155454A
Authority
JP
Japan
Prior art keywords
memory
register
contents
given
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5905380A
Other languages
Japanese (ja)
Inventor
Kenji Kuroda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5905380A priority Critical patent/JPS56155454A/en
Publication of JPS56155454A publication Critical patent/JPS56155454A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To improve the test efficiency without increasing the amount of hardware, by using a storage element in stead of a check register, a comparator, and a discriminator. CONSTITUTION:Before the start of the test, for example, the pattern shown in the figure is counted up from ''0'' by +1 successively in the address counter, and selecting circuit 13 is set to select the output of address counter 12, and write data 17 and write pulse 18 are given to memory element 15 by control circuit 19. After the completion of this operation, selecting circuit 13 is set to select the output of memory address register 2, and programs are executed successively. Contents of memory address register 2 are given to storage element 15 at every memory access, and read data of the output is given to control circuit 5. Only contents of address ''A'' are ''1'' in memory element 15; and only when the memory is accessed with ''A'' of contents of register 2, read data 19 becomes ''1'', and execution of instructions is stopped or an interruption is caused to occur by control circuit 5.
JP5905380A 1980-05-02 1980-05-02 Test controller for program Pending JPS56155454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5905380A JPS56155454A (en) 1980-05-02 1980-05-02 Test controller for program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5905380A JPS56155454A (en) 1980-05-02 1980-05-02 Test controller for program

Publications (1)

Publication Number Publication Date
JPS56155454A true JPS56155454A (en) 1981-12-01

Family

ID=13102191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5905380A Pending JPS56155454A (en) 1980-05-02 1980-05-02 Test controller for program

Country Status (1)

Country Link
JP (1) JPS56155454A (en)

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