JPS56137628A - Pattern forming - Google Patents

Pattern forming

Info

Publication number
JPS56137628A
JPS56137628A JP4089580A JP4089580A JPS56137628A JP S56137628 A JPS56137628 A JP S56137628A JP 4089580 A JP4089580 A JP 4089580A JP 4089580 A JP4089580 A JP 4089580A JP S56137628 A JPS56137628 A JP S56137628A
Authority
JP
Japan
Prior art keywords
pattern
mask
space
constitution
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4089580A
Other languages
Japanese (ja)
Other versions
JPS6310890B2 (en
Inventor
Masaki Ito
Sotaro Edokoro
Hiroshi Gokan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4089580A priority Critical patent/JPS56137628A/en
Publication of JPS56137628A publication Critical patent/JPS56137628A/en
Publication of JPS6310890B2 publication Critical patent/JPS6310890B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Bipolar Transistors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a pattern having microlinear width by providing a forming mask for the second pattern to be overlapped on the first pattern of line and space in the form of such second pattern as to allow the alignment at a prearranged space of pellets having an element unit of the same forms of the first and second patterns. CONSTITUTION:The first pattern of line and space is provided on a resist 3 on a sample 1, and then is coated with another resist 11 on the first pattern to be covered by an exposure mask 61. The mask 61 has plural pellets 62 and patterns 64, 65 of the same form. The said mask is aligned at a space of (2n-1)l with half the repetitive period of the first pattern. If the rotary deviation of the mask 61 and the first pattern is removed and they are subjected to exposure and development, and the mask is removed after the sample was etched with the resists 3, 11 used as a mask, a good-quality product 69 and an inferior-quality product 70 are generated in a chip 66. Under this constitution, it is possible to form a pattern having high precision linear width enabling the availability of chips whose quality is double the conventional-type chip only by correcting a rotary deviation.
JP4089580A 1980-03-28 1980-03-28 Pattern forming Granted JPS56137628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4089580A JPS56137628A (en) 1980-03-28 1980-03-28 Pattern forming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4089580A JPS56137628A (en) 1980-03-28 1980-03-28 Pattern forming

Publications (2)

Publication Number Publication Date
JPS56137628A true JPS56137628A (en) 1981-10-27
JPS6310890B2 JPS6310890B2 (en) 1988-03-10

Family

ID=12593240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4089580A Granted JPS56137628A (en) 1980-03-28 1980-03-28 Pattern forming

Country Status (1)

Country Link
JP (1) JPS56137628A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252165A (en) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc Pattern forming method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252165A (en) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc Pattern forming method
JP4480424B2 (en) * 2004-03-08 2010-06-16 富士通マイクロエレクトロニクス株式会社 Pattern formation method

Also Published As

Publication number Publication date
JPS6310890B2 (en) 1988-03-10

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