JPS56134377A - Storage device - Google Patents

Storage device

Info

Publication number
JPS56134377A
JPS56134377A JP3646880A JP3646880A JPS56134377A JP S56134377 A JPS56134377 A JP S56134377A JP 3646880 A JP3646880 A JP 3646880A JP 3646880 A JP3646880 A JP 3646880A JP S56134377 A JPS56134377 A JP S56134377A
Authority
JP
Japan
Prior art keywords
address
line
contents
rom
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3646880A
Other languages
Japanese (ja)
Inventor
Koichi Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3646880A priority Critical patent/JPS56134377A/en
Publication of JPS56134377A publication Critical patent/JPS56134377A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615Address space extension
    • G06F12/0623Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To expand the use range of ROM by reading the contents of ROM and RAM simultaneously by using the same address and by writing data in only RAM. CONSTITUTION:Decoders 11 and 21 are connected to common address assignment line 5. To read one word in assigned address A, the binary number that corresponds to address A is applied to line 5 and a pulse of logic ''1'' is applied to readable line 6 to store the contents of address A of ROM12 by using the 1st-(B0)-th bits of read register 3 and those of address A of ROM22 by using the (B0+1)-th bit-(Ba)-th bit respectively. To rewrite the contents of address A of RAM22, data is set in write register 4, the binary number that corresponds to address A is applied to line 5, and a pulse of logic ''1'' is also applied to writable line 7.
JP3646880A 1980-03-21 1980-03-21 Storage device Pending JPS56134377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3646880A JPS56134377A (en) 1980-03-21 1980-03-21 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3646880A JPS56134377A (en) 1980-03-21 1980-03-21 Storage device

Publications (1)

Publication Number Publication Date
JPS56134377A true JPS56134377A (en) 1981-10-21

Family

ID=12470638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3646880A Pending JPS56134377A (en) 1980-03-21 1980-03-21 Storage device

Country Status (1)

Country Link
JP (1) JPS56134377A (en)

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