JPS56132042A - Continuous clock generating system - Google Patents

Continuous clock generating system

Info

Publication number
JPS56132042A
JPS56132042A JP3489480A JP3489480A JPS56132042A JP S56132042 A JPS56132042 A JP S56132042A JP 3489480 A JP3489480 A JP 3489480A JP 3489480 A JP3489480 A JP 3489480A JP S56132042 A JPS56132042 A JP S56132042A
Authority
JP
Japan
Prior art keywords
clocks
pulses
frequency division
frequency
alpha
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3489480A
Other languages
Japanese (ja)
Other versions
JPS6058621B2 (en
Inventor
Shintarou Azami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55034894A priority Critical patent/JPS6058621B2/en
Publication of JPS56132042A publication Critical patent/JPS56132042A/en
Publication of JPS6058621B2 publication Critical patent/JPS6058621B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain continuous clocks phase-synchronized with burst clocks by giving burst clocks directly as the phase synchronizing circuit input to obtain clocks. CONSTITUTION:Frequency division ratios of the first and the second frequency dividers 1 and 2 are selected to make alpha.N=P-Q=R true. (alpha: an integer). If the number of pulses per one frame is denoted as Q=qN+rq and P=pN+rp, respectivly (p and q are positive integers, and rp and rq are positive intergers <=N), rp=rq and alpha=p-q are satisfied by the frequency division ratio condition. That is, when clocks are divided by frequency dividers 1 and 2 q-number and p-number pulses are outputted for every N pulses. Consequently, in the next frame, the time shifted by (N-r)-pulse components becomes the N frequency division pulse output point for both dividers. Thus, rises or falls of N-frequency division pulses are always caused to coincide with each other. The phase difference is detected by phase comparator 3 to control the oscillation frequency of VCO 5.
JP55034894A 1980-03-21 1980-03-21 Continuous clock generation method Expired JPS6058621B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55034894A JPS6058621B2 (en) 1980-03-21 1980-03-21 Continuous clock generation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55034894A JPS6058621B2 (en) 1980-03-21 1980-03-21 Continuous clock generation method

Publications (2)

Publication Number Publication Date
JPS56132042A true JPS56132042A (en) 1981-10-16
JPS6058621B2 JPS6058621B2 (en) 1985-12-20

Family

ID=12426869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55034894A Expired JPS6058621B2 (en) 1980-03-21 1980-03-21 Continuous clock generation method

Country Status (1)

Country Link
JP (1) JPS6058621B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472640A (en) * 1987-09-14 1989-03-17 Nec Corp Digital data smoothing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472640A (en) * 1987-09-14 1989-03-17 Nec Corp Digital data smoothing circuit

Also Published As

Publication number Publication date
JPS6058621B2 (en) 1985-12-20

Similar Documents

Publication Publication Date Title
KR840005000A (en) Horizontal scan frequency multiplication circuit
FI88567C (en) A synchronous 2N + 1 divider is generated
CA1216032A (en) Variable digital frequency generator with value storage
JPS56132042A (en) Continuous clock generating system
KR890012482A (en) Synchronous separation circuit
JPS57164689A (en) Pal system synchronizing signal generator
SU866748A1 (en) Pulse rate scaler
US3701026A (en) Median frequency generator
SU1142889A1 (en) Pulse repetition frequency multiplier
GB1301840A (en)
SU569001A1 (en) Controlled digital frequency divider for phase-wise automatic frequency adjustment system
SU915264A1 (en) Digital device for monitoring binary train delay
SU580647A1 (en) Frequensy divider with fractional division factor
KR0144281B1 (en) Cluck generator
SU964984A1 (en) Digital frequency synthesizer
SU446940A1 (en) Frequency multiplier
SU1252940A1 (en) Digital frequency synthesizer
SU777824A1 (en) Retunable pulse repetition frequency divider
RU1815803C (en) Digital generator of signals manipulated by minimal shift
KR940012090A (en) Clock divider
SU1215185A1 (en) Synchronizing device with phase-lock control
SU495771A1 (en) Digital device frequency tuning controlled oscillators
SU1107260A2 (en) Digital frequency synthesizer
SU694982A1 (en) Synchronization arrangement
JPS61245648A (en) Injection synchronous type pulse generating circuit