JPS56129339A - Method of manufacturing semiconductor integrated circuit device - Google Patents
Method of manufacturing semiconductor integrated circuit deviceInfo
- Publication number
- JPS56129339A JPS56129339A JP3303580A JP3303580A JPS56129339A JP S56129339 A JPS56129339 A JP S56129339A JP 3303580 A JP3303580 A JP 3303580A JP 3303580 A JP3303580 A JP 3303580A JP S56129339 A JPS56129339 A JP S56129339A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- integrated circuit
- semiconductor integrated
- circuit device
- manufacturing semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To increase the degree of current amplification by a method wherein an emitter layer of a vertical transistor is formed simultaneously with the diffusion process for one or separation layers at both sides. CONSTITUTION:A p emitter 3a is formed on an n<-> epitaxial layer 2 having been developed on a p<+> type Si substrate 1, simultaneously with p<+> emitters at the upper side. By so doing, the p emitter 3a can be formed to have a sufficient depth and hence to make a base width WB2 smaller, whereby the degree of current amplification for a vertical p-n-p transistor is increased. In addition, the high frequency characteristic is also improved due to the reduced base width.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3303580A JPS56129339A (en) | 1980-03-12 | 1980-03-12 | Method of manufacturing semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3303580A JPS56129339A (en) | 1980-03-12 | 1980-03-12 | Method of manufacturing semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56129339A true JPS56129339A (en) | 1981-10-09 |
Family
ID=12375529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3303580A Pending JPS56129339A (en) | 1980-03-12 | 1980-03-12 | Method of manufacturing semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56129339A (en) |
-
1980
- 1980-03-12 JP JP3303580A patent/JPS56129339A/en active Pending
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