JPS56125853A - Semiconductor circuit device - Google Patents

Semiconductor circuit device

Info

Publication number
JPS56125853A
JPS56125853A JP2834380A JP2834380A JPS56125853A JP S56125853 A JPS56125853 A JP S56125853A JP 2834380 A JP2834380 A JP 2834380A JP 2834380 A JP2834380 A JP 2834380A JP S56125853 A JPS56125853 A JP S56125853A
Authority
JP
Japan
Prior art keywords
conductor layer
high frequency
conductor
layer
semiconductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2834380A
Other languages
Japanese (ja)
Other versions
JPS6033313B2 (en
Inventor
Norio Matsui
Taichi Kon
Takaaki Osaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2834380A priority Critical patent/JPS6033313B2/en
Publication of JPS56125853A publication Critical patent/JPS56125853A/en
Publication of JPS6033313B2 publication Critical patent/JPS6033313B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce unnecessary consumption of power source by a method wherein a conductive layer is formed on a main surface of the reverce side of a monocrystalline substrate having a high conductivity to supply the power source to circuit elements. CONSTITUTION:A conductor layer PL is formed on one side of the monocrystalline substrate B by a high frequency spattering of an Al-Cu alloy, and conductor layers PLL1 AND PLL2 are formed on a main surface M by high frequency spattering of Mo and Au. Then, an insulating layer I1 and a conductor layer GL are formed by high frequency spattering of SiO2 and the Al-Cu alloy, and the conductor layer GL is made a prescribed shape by a photoetching. After insulating layers I2, I3, I4 and conductor layers SL1, SL2 having been formed by repeating the same process, a through hole is formed and an electrode connecting each conductor layer is formed. Subsequently, a semiconductor circuit element Q is mounted to be connected with a lead. Accordingly, the current flows through the substrate B and is not consumed unnecessarily.
JP2834380A 1980-03-06 1980-03-06 semiconductor circuit device Expired JPS6033313B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2834380A JPS6033313B2 (en) 1980-03-06 1980-03-06 semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2834380A JPS6033313B2 (en) 1980-03-06 1980-03-06 semiconductor circuit device

Publications (2)

Publication Number Publication Date
JPS56125853A true JPS56125853A (en) 1981-10-02
JPS6033313B2 JPS6033313B2 (en) 1985-08-02

Family

ID=12245946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2834380A Expired JPS6033313B2 (en) 1980-03-06 1980-03-06 semiconductor circuit device

Country Status (1)

Country Link
JP (1) JPS6033313B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856447A (en) * 1981-09-11 1983-04-04 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Identification card and method of producing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856447A (en) * 1981-09-11 1983-04-04 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Identification card and method of producing same

Also Published As

Publication number Publication date
JPS6033313B2 (en) 1985-08-02

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