JPS6461038A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6461038A
JPS6461038A JP21941887A JP21941887A JPS6461038A JP S6461038 A JPS6461038 A JP S6461038A JP 21941887 A JP21941887 A JP 21941887A JP 21941887 A JP21941887 A JP 21941887A JP S6461038 A JPS6461038 A JP S6461038A
Authority
JP
Japan
Prior art keywords
layer
bump
opening
deposited
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21941887A
Other languages
Japanese (ja)
Other versions
JPH0715909B2 (en
Inventor
Yoshiyuki Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21941887A priority Critical patent/JPH0715909B2/en
Publication of JPS6461038A publication Critical patent/JPS6461038A/en
Publication of JPH0715909B2 publication Critical patent/JPH0715909B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To alleviate an internal stress due to soldering and to suppress a decrease in antioxidation performance due to a crack by suppressing the diffusion of tin in a copper layer by interposing a lead layer between a bump of copper and a soldering layer of its surface. CONSTITUTION:A metal layer is deposited on an insulating film 2 provided on a semiconductor substrate 1, and selectively etched to form an electrode pad 3. An interlayer insulating film 4 is provided, a first opening 5 is formed on the pad 3, and, first and second metal layers 6, 7 are sequentially deposited on the surface. Then, a photoresist film 8 is provided, patterned, and a second opening 9 slightly larger than the opening 5 is formed. A copper layer is deposited on the layer 7 of the opening 9 by an electrically plating method, and a bump 10 is formed on the film 8. A lead layer 11 is plated on the bump 10. and a solder plating layer 12 is formed on the surface. With the bump 10 as a mask the layers 6, 7 are sequentially etched and removed.
JP21941887A 1987-09-01 1987-09-01 Method for manufacturing semiconductor device Expired - Lifetime JPH0715909B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21941887A JPH0715909B2 (en) 1987-09-01 1987-09-01 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21941887A JPH0715909B2 (en) 1987-09-01 1987-09-01 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6461038A true JPS6461038A (en) 1989-03-08
JPH0715909B2 JPH0715909B2 (en) 1995-02-22

Family

ID=16735083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21941887A Expired - Lifetime JPH0715909B2 (en) 1987-09-01 1987-09-01 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0715909B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997003465A1 (en) * 1995-07-12 1997-01-30 Hitachi, Ltd. Semiconductor pellet, method of its packaging, and bump electrode
WO2017110326A1 (en) 2015-12-25 2017-06-29 昭和電工株式会社 Curable composition, cured object, overcoat film, coated flexible wiring board, and process for producing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997003465A1 (en) * 1995-07-12 1997-01-30 Hitachi, Ltd. Semiconductor pellet, method of its packaging, and bump electrode
WO2017110326A1 (en) 2015-12-25 2017-06-29 昭和電工株式会社 Curable composition, cured object, overcoat film, coated flexible wiring board, and process for producing same

Also Published As

Publication number Publication date
JPH0715909B2 (en) 1995-02-22

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