KR20000043575A - Chip sized package having capacitor and fabrication method thereof - Google Patents

Chip sized package having capacitor and fabrication method thereof Download PDF

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Publication number
KR20000043575A
KR20000043575A KR1019980059973A KR19980059973A KR20000043575A KR 20000043575 A KR20000043575 A KR 20000043575A KR 1019980059973 A KR1019980059973 A KR 1019980059973A KR 19980059973 A KR19980059973 A KR 19980059973A KR 20000043575 A KR20000043575 A KR 20000043575A
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South Korea
Prior art keywords
insulating film
capacitor
metal pattern
pad
electrode
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KR1019980059973A
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Korean (ko)
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KR100431307B1 (en
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김재면
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김영환
현대전자산업 주식회사
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Priority to KR10-1998-0059973A priority Critical patent/KR100431307B1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE: A chip sized package having a capacitor and a fabrication method thereof are provided to improve a mounting density of the package to a mother board. CONSTITUTION: A first insulating layer(21) is coated on a semiconductor chip(10) but pads(11) centrally formed on the chip(10) are exposed. First metal patterns(31) are deposited on the insulating layer(21) so that first end of each metal pattern(31) is connected with each pad(11). A second insulating layer(22) is coated on the first insulating layer(21) while covering almost the first metal patterns(31) but exposing second end of each metal pattern(31). A capacitor having electrodes(42) on a die(41) is formed on the second insulating layer(22) above the pads(11). A third insulating layer(23) covers the capacitor except the electrode(42). Second metal patterns(32) are connected with the electrode(42) at first ends thereof and connected with the second ends of the first metal patterns(31) at second ends thereof. A fourth insulating layer(24) is formed on overall surfaces but exposing the second ends(i.e., ball lands) of the second metal patterns(32). After solder paste is applied to the ball lands, solder balls(51) are mounted on the solder paste.

Description

캐패시터 내장형 칩 사이즈 패키지 및 그의 제조 방법Capacitor embedded chip size package and manufacturing method thereof

본 발명은 캐패시터 내장형 칩 사이즈 패키지 및 그의 제조 방법에 관한 것으로서, 보다 구체적으로는 캐패시터가 일체로 구성된 칩 사이즈 패키지 및 이를 제조하는 방법에 관한 것이다.The present invention relates to a chip size package with a built-in capacitor, and more particularly, to a chip size package in which a capacitor is integrally formed and a method for manufacturing the same.

칩 사이즈 패키지는 패키지의 크기를 칩의 크기로 설정할 수 있다는 장점이 있기 때문에, 경박단소화되는 패키지 경향에 따라 연구가 계속되고 있는 추세이다. 이러한 칩 사이즈 패키지는 휘어지지 않는 강체의 기판을 이용하거나, 또는 패턴 테이프를 이용하는 방식 등이 있다.Chip size packages have the advantage that the size of the package can be set to the size of the chip, research is being continued in accordance with the trend of light and short package. Such a chip size package uses a rigid substrate, or a pattern tape.

상기 방식들 중에서 기판을 이용한 방식은, 기판 제작이 매우 난해하기 때문에, 패턴 테이프를 이용하는 방식이 최근에 주로 제시되고 있다. 패턴 테이프는 패터닝된 금속 라인을 갖는 테이프로서, 이러한 패턴 테이프를 이용한 종래의 칩 사이즈 패키지의 구조를 도 1을 참고로 하여 개략적으로 설명하면 다음과 같다.Among the above methods, a method using a substrate is very difficult to manufacture a substrate, and thus, a method using a pattern tape has been mainly proposed in recent years. The pattern tape is a tape having a patterned metal line. The structure of a conventional chip size package using the pattern tape will be described below with reference to FIG. 1.

도시된 바와 같이, 반도체 칩(1)이 패턴 테이프(2)의 표면에 완충제(3)를 매개로 접착되어 있다. 패턴 테이프(2)의 금속 배선이 금속 와이어(7)에 의해 반도체 칩(1)의 패드(1a)에 전기적으로 연결되어 있다. 반도체 칩(1)의 하부는 봉지제(4)로 몰딩되어 있고, 봉지제(4)에서 노출된 패턴 테이프(2)의 밑면에는 솔더 볼(8)들이 마운트되어 있다.As shown in the drawing, the semiconductor chip 1 is adhered to the surface of the pattern tape 2 via the buffer 3. The metal wiring of the pattern tape 2 is electrically connected to the pad 1a of the semiconductor chip 1 by the metal wire 7. The lower portion of the semiconductor chip 1 is molded with an encapsulant 4, and solder balls 8 are mounted on the bottom surface of the pattern tape 2 exposed from the encapsulant 4.

솔더 볼(8)이 기판(5:PCB)에 실장되는데, 기판(5)에는 캐패시터(6)가 실장될 경우도 있다. 즉, 캐패시터(6)는 기판(5)에 실장되어서, 기판(5)에 구비된 금속 라인(5a)을 통해 솔더 볼(8)과 전기적으로 연결되어 있다.The solder ball 8 is mounted on the board | substrate 5: PCB, but the capacitor 6 may be mounted on the board | substrate 5 in some cases. That is, the capacitor 6 is mounted on the board | substrate 5, and is electrically connected with the solder ball 8 through the metal line 5a with which the board | substrate 5 was equipped.

그런데, 종래에는 패키지와 캐패시터가 별도로 구성되어서 각각을 기판에 실장해야 하므로, 기판의 고집적도를 실현할 수가 없었다. 또한, 패키지와 캐패시터를 연결하기 위해서, 기판에 금속 라인을 설계해야 하므로, 이로 인하여 기판의 금속 라인이 매우 복잡해진다는 문제점이 있다.By the way, since a package and a capacitor are comprised separately and each must be mounted in a board | substrate, high integration of a board | substrate was not realizable. In addition, in order to connect the package and the capacitor, a metal line must be designed on the substrate, which causes a problem that the metal line of the substrate becomes very complicated.

따라서, 본 발명은 상기된 문제점을 해소하기 위해 안출된 것으로서, 패키지 내부에 캐패시터를 일체로 구성시켜서, 기판의 고집적도가 실현되고 아울러 기판의 금속 라인 구조가 복잡해지지 않는 캐패시터 내장형 칩 사이즈 캐패시터 및 그의 제조 방법을 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the above-described problem, by integrating a capacitor inside the package, the high integration of the substrate is realized and the chip embedded capacitor size capacitor and the metal line structure of the substrate is not complicated and its It is an object to provide a manufacturing method.

도 1은 캐패시터와 패키지가 각각 기판에 실장된 구조를 나타낸 도면1 is a view showing a structure in which a capacitor and a package are mounted on a substrate, respectively

도 2 내지 도 13은 본 발명의 실시예 1에 따른 칩 사이즈 패키지를 제조 공정 순서대로 나타낸 도면2 to 13 illustrate chip size packages according to Embodiment 1 of the present invention in the order of manufacturing process;

도 14는 본 발명의 실시예 2에 따른 칩 사이즈 패키지를 나타낸 도면14 illustrates a chip size package according to Embodiment 2 of the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

10 ; 반도체 칩 11 ; 패드10; Semiconductor chip 11; pad

21 ; 제 1 절연막 22 ; 제 2 절연막21; 1st insulating film 22; Second insulating film

23 ; 제 3 절연막 24 ; 제 4 절연막23; Third insulating film 24; Fourth insulating film

25 ; 볼 랜드 31 ; 제 1 금속 패턴25; Boland 31; First metal pattern

32 ; 제 2 금속 패턴 40 ; 캐패시터32; Second metal pattern 40; Capacitor

41 ; 다이 42 ; 전극41; Die 42; electrode

50 ; 솔더 페이스트 51 ; 솔더 볼50; Solder paste 51; Solder ball

상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 칩 사이즈 패키지는 다음과 같은 구성으로 이루어진다.In order to achieve the above object, the chip size package according to the present invention has the following configuration.

반도체 칩의 표면에 패드가 노출되도록 제 1 절연막이 도포된다. 일단이 노출된 패드와 연결되도록, 제 1 금속 패턴이 제 1 절연막 표면에 증착된다. 제 1 금속 패턴의 타단이 노출되도록, 전체 구조 상부에 제 2 절연막이 도포된다. 패드 상부의 제 2 절연막 표면에 캐패시터가 접착된다. 캐패시터의 전극이 노출되도록, 캐패시터에 제 3 절연막이 도포된다. 캐패시터의 전극과 제 1 금속 패턴의 타단이 제 2 금속 패턴에 의해 연결된다. 제 1 금속 패턴의 타단과 연결된 제 2 금속 패턴 부분이 노출되어 볼 랜드가 형성되도록, 전체 구조 상부에 제 4 절연막이 도포된다. 볼 랜드에 솔더 페이스트가 도포되고, 솔더 볼이 솔더 페이스트에 마운트된다.The first insulating film is coated so that the pad is exposed on the surface of the semiconductor chip. A first metal pattern is deposited on the surface of the first insulating film so that one end is connected to the exposed pad. A second insulating film is applied over the entire structure so that the other end of the first metal pattern is exposed. A capacitor is bonded to the surface of the second insulating film on the pad. The third insulating film is applied to the capacitor so that the electrode of the capacitor is exposed. The electrode of the capacitor and the other end of the first metal pattern are connected by the second metal pattern. A fourth insulating film is applied over the entire structure so that the second metal pattern portion connected to the other end of the first metal pattern is exposed to form a ball land. Solder paste is applied to the ball lands, and the solder balls are mounted on the solder paste.

상기와 같은 구조로 이루어진 칩 사이즈 패키지를 제조하는 방법은 다음과 같은 단계로 이루어진다.The method of manufacturing a chip size package having the above structure consists of the following steps.

복수개의 반도체 칩이 구성된 웨이퍼 표면에 제 1 절연막을 도포하고, 각 반도체 칩의 패드가 노출되도록 제 1 절연막의 해당 부분을 식각한다. 노출된 패드와 일단이 연결되도록 제 1 금속 패턴들을 제 1 절연막 표면에 증착한다. 전체 구조 상부에 제 2 절연막을 도포하고, 제 1 금속 패턴의 타단이 노출되도록 제 2 절연막의 해당 부분을 식각한다. 전극이 상부를 향하게 캐패시터를 패드 상부의 제 2 절연막 표면에 접착한다. 전극이 노출되도록 캐패시터 주위에 제 3 절연막을 도포하고, 제 2 및 제 3 절연막에 제 2 금속 패턴을 증착하여, 전극과 제 1 금속 패턴을 전기적으로 연결시킨다. 전체 구조 상부에 제 4 절연막을 도포하고, 제 1 금속 패턴과 연결된 제 2 금속 패턴이 노출되어 볼 랜드가 형성되도록, 제 4 절연막의 해당 부분을 식각한다. 볼 랜드에 솔더 페이스트를 도포하고, 솔더 볼을 솔더 페이스트에 마운트한 다음, 웨이퍼를 스크라이브 라인을 따라 절단하여 개개의 반도체 칩들로 분리한다.The first insulating film is coated on the surface of the wafer including the plurality of semiconductor chips, and the corresponding portion of the first insulating film is etched to expose the pad of each semiconductor chip. First metal patterns are deposited on the surface of the first insulating layer so that the exposed pad and one end thereof are connected to each other. A second insulating film is coated on the entire structure, and a corresponding portion of the second insulating film is etched to expose the other end of the first metal pattern. The capacitor is adhered to the surface of the second insulating film above the pad with the electrode facing upwards. A third insulating film is coated around the capacitor to expose the electrode, and a second metal pattern is deposited on the second and third insulating films to electrically connect the electrode and the first metal pattern. A fourth insulating film is coated on the entire structure, and a corresponding portion of the fourth insulating film is etched to expose a second metal pattern connected to the first metal pattern to form a ball land. Solder paste is applied to the ball lands, the solder balls are mounted on the solder paste, and the wafer is cut along the scribe line to separate the individual semiconductor chips.

상기된 본 발명의 구성에 의하면, 캐패시터가 패키지 내부에 일체로 구성되어서 함께 기판에 실장되게 되므로써, 기판의 고집적도가 실현되고 기판의 금속 라인 설계도 복잡해지지 않게 된다.According to the above-described configuration of the present invention, since the capacitor is integrally formed inside the package and mounted on the substrate together, high integration of the substrate is realized and the metal line design of the substrate is not complicated.

이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

[실시예 1]Example 1

도 2 내지 도 13은 본 발명의 실시예 1에 따른 칩 사이즈 패키지를 제조 공정 순서대로 나타낸 도면이다.2 to 13 is a view showing a chip size package according to a first embodiment of the present invention in the order of manufacturing process.

먼저, 도 2에 도시된 바와 같이, 복수개의 반도체 칩(10)이 구성된 웨이퍼 표면에 제 1 절연막(21)을 도포한다. 특히, 본 실시예 1에 적용되는 반도체 칩(10)은 패드(11)가 중앙에 배치된다. 패드(11)가 노출되도록, 제 1 절연막(21)의 해당 부분을 식각한다.First, as shown in FIG. 2, the first insulating film 21 is coated on the wafer surface on which the plurality of semiconductor chips 10 are formed. In particular, in the semiconductor chip 10 according to the first embodiment, the pad 11 is disposed at the center. The corresponding portion of the first insulating film 21 is etched to expose the pad 11.

이어서, 도 3a 및 도 3b에 도시된 바와 같이, 제 1 절연막(21) 표면에 제 1 금속 패턴(31)을 증착하여, 노출된 패드(11)에 일단이 연결되고, 타단은 볼 랜드(25) 부분에 연결한다. 패드(11)에는 금속 패턴(31)과의 전기적 부착력 강화를 위해, 구리/니켈/금, 구리/니켈/크롬/금, 구리/니켈/코발트/금, 구리/니켈/금/주석, 구리/니켈/크롬/금/주석, 또는 구리/니켈/코발트/금/주석 중 어느 한 합금이 도금되는 것이 바람직하고, 제 1 금속 패턴(31)의 재질로는 금, 은, 니켈, 인듐, 주석 중의 하나를 사용할 수가 있다. 그런 다음, 도 4와 같이 전체 구조 상부에 제 2 절연막(22)을 도포하고, 제 1 금속 패턴(31)의 타단이 노출되도록 제 2 절연막(22)의 해당 부분을 식각한다.3A and 3B, the first metal pattern 31 is deposited on the surface of the first insulating layer 21 so that one end is connected to the exposed pad 11 and the other end is a ball land 25. ) Part. The pad 11 has copper / nickel / gold, copper / nickel / chrome / gold, copper / nickel / cobalt / gold, copper / nickel / gold / tin, and copper / for enhanced electrical adhesion with the metal pattern 31. Nickel / chromium / gold / tin, or copper / nickel / cobalt / gold / tin is preferably plated with an alloy, and the material of the first metal pattern 31 is gold, silver, nickel, indium, tin. You can use one. Next, as shown in FIG. 4, the second insulating layer 22 is coated on the entire structure, and the corresponding portion of the second insulating layer 22 is etched to expose the other end of the first metal pattern 31.

이어서, 도 5와 같은 다이(41)와 전극(42)으로 구성된 캐패시터(40)를 준비하고, 도 6과 같이, 전극(42)이 상부를 향하게 캐패시터(40)를 패드(11) 상부의 제 2 절연막(22) 표면에 접착한다. 그런 다음, 도 7과 같이 전극(42)이 노출되도록 다이(41) 주위에 제 3 절연막(23)을 도포한다.Subsequently, a capacitor 40 including a die 41 and an electrode 42 as shown in FIG. 5 is prepared, and as shown in FIG. 6, the capacitor 40 is placed on the upper side of the pad 11 with the electrode 42 facing upward. 2 Adhesion to the surface of the insulating film 22. Then, a third insulating film 23 is applied around the die 41 to expose the electrode 42 as shown in FIG.

이어서, 도 8과 같이 제 2 및 제 3 절연막(22,23) 부분에 제 1 금속 패턴(31)과 동일 재질의 제 2 금속 패턴(32)을 증착하여, 캐패시터(40)의 전극(42)과 제 1 금속 패턴(31)의 타단을 전기적으로 연결시킨다.Subsequently, as shown in FIG. 8, the second metal pattern 32 having the same material as the first metal pattern 31 is deposited on the second and third insulating layers 22 and 23 to form the electrode 42 of the capacitor 40. And the other end of the first metal pattern 31 are electrically connected to each other.

그런 다음, 도 9에 도시된 바와 같이, 캐패시터(40)가 완전히 차단되도록 전체 구조 상부에 제 4 절연막(24)을 도포하고, 도 10과 같이 제 1 금속 패턴(31)의 타단이 노출되도록 제 4 절연막(24)의 해당 부분을 식각하여 볼 랜드(25)를 형성한다.Then, as shown in FIG. 9, the fourth insulating film 24 is coated on the entire structure so that the capacitor 40 is completely blocked, and the other end of the first metal pattern 31 is exposed as shown in FIG. 10. 4 A corresponding portion of the insulating film 24 is etched to form a ball land 25.

이어서, 도 11과 같이, 볼 랜드(25)에 솔더 페이스트(50)를 도포하여 볼 랜드(25)를 완전히 매립하고, 도 12와 같이 각 솔더 페이스(50)에 솔더 볼(51)을 마운트하여 리플로우시킨다. 마지막으로, 웨이퍼를 스크라이브 라인을 따라 절단하면, 도 13과 같이 캐패시터(40)가 내장된 칩 사이즈 패키지들이 개개로 완성된다.Subsequently, as shown in FIG. 11, the solder paste 50 is applied to the ball lands 25 to completely fill the ball lands 25, and as shown in FIG. 12, the solder balls 51 are mounted to the solder faces 50. Reflow. Finally, when the wafer is cut along the scribe line, the chip size packages in which the capacitor 40 is embedded are completed as shown in FIG. 13.

[실시예 2]Example 2

도 14는 본 발명의 실시예 2에 따른 칩 사이즈 패키지를 나타낸 단면도로서, 도시된 바와 같이, 모든 구조가 실시예 1과 거의 동일하고, 다만 반도체 칩(10)의 패드(11)가 중앙이 아니라 양측에 배치된 것만 상이하다. 따라서, 실시예 2에 따른 패키지를 제조하는 방법은 실시예 1과 동일하므로, 반복 설명은 생략한다.FIG. 14 is a cross-sectional view showing a chip size package according to Embodiment 2 of the present invention. As shown, all structures are substantially the same as those of Embodiment 1, except that the pad 11 of the semiconductor chip 10 is not centered. Only those arranged on both sides are different. Therefore, since the method of manufacturing the package according to the second embodiment is the same as that of the first embodiment, a repetitive description is omitted.

이상에서 설명한 바와 같이 본 발명에 의하면, 캐패시터가 패키지에 일체로 내장되어서 기판에 함께 실장되므로써, 기판의 고집적도가 구현될 수가 있게 되고 아울러 기판의 금속 라인 설계도 복잡해지지 않게 된다.As described above, according to the present invention, since the capacitor is integrally embedded in the package and mounted together on the substrate, high integration of the substrate can be realized and the metal line design of the substrate is not complicated.

이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.

Claims (4)

패드가 상부를 향하게 배치된 반도체 칩;A semiconductor chip having a pad facing upward; 상기 패드가 노출되도록, 상기 반도체 칩의 표면에 도포된 제 1 절연막;A first insulating film coated on a surface of the semiconductor chip so that the pad is exposed; 일단이 상기 패드에 연결되게, 상기 제 1 절연막 표면에 증착된 제 1 금속 패턴;A first metal pattern deposited on a surface of the first insulating layer so that one end is connected to the pad; 상기 제 1 금속 패턴의 타단이 노출되도록, 전체 구조 상부에 도포된 제 2 절연막;A second insulating film coated on the entire structure so that the other end of the first metal pattern is exposed; 상기 패드 상부의 제 2 절연막 표면에 전극이 상부를 향하게 접착된 캐패시터;A capacitor having an electrode bonded upward to a surface of a second insulating film on the pad; 상기 전극이 노출되도록, 캐패시터에 도포된 제 3 절연막;A third insulating film coated on the capacitor to expose the electrode; 상기 캐패시터의 전극과 제 1 금속 패턴의 타단을 전기적으로 연결하는 제 2 금속 패턴;A second metal pattern electrically connecting an electrode of the capacitor and the other end of the first metal pattern; 상기 제 1 금속 패턴의 타단이 노출되어 볼 랜드가 형성되도록, 전체 구조 상부에 도포된 제 4 절연막;A fourth insulating film coated on the entire structure so that the other end of the first metal pattern is exposed to form a ball land; 상기 볼 랜드에 도포된 솔더 페이스트; 및A solder paste applied to the ball lands; And 상기 솔더 페이스트에 마운트된 솔더 볼을 포함하는 캐패시터 내장형 칩 사이즈 패키지.Chip size package with a capacitor containing a solder ball mounted to the solder paste. 제 1 항에 있어서, 상기 제 1 및 제 2 금속 패턴의 재질은 금, 은, 니켈, 인듐, 또는 주석 중의 하나인 것을 특징으로 하는 캐패시터 내장형 칩 사이즈 패키지.The chip size package according to claim 1, wherein the first and second metal patterns are made of gold, silver, nickel, indium, or tin. 제 1 항에 있어서, 상기 패드에 구리/니켈/금, 구리/니켈/크롬/금, 구리/니켈/코발트/금, 구리/니켈/금/주석, 구리/니켈/크롬/금/주석, 또는 구리/니켈/코발트/금/주석 중 어느 한 합금이 도금된 것을 특징으로 하는 캐패시터 내장형 칩 사이즈 패키지.The method of claim 1, wherein the pad includes copper / nickel / gold, copper / nickel / chrome / gold, copper / nickel / cobalt / gold, copper / nickel / gold / tin, copper / nickel / chrome / gold / tin, or Chip size package with a built-in capacitor, characterized in that the plating of any one of copper / nickel / cobalt / gold / tin. 복수개의 반도체 칩이 구성된 웨이퍼 표면에 제 1 절연막을 도포하고, 상기 반도체 칩의 패드가 노출되도록 제 1 절연막의 해당 부분을 식각하는 단계;Applying a first insulating film to a surface of a wafer including a plurality of semiconductor chips, and etching a corresponding portion of the first insulating film to expose a pad of the semiconductor chip; 상기 제 1 절연막 표면에 제 1 금속 패턴을 증착하여, 상기 제 1 금속 패턴의 일단을 노출된 패드에 연결시키는 단계;Depositing a first metal pattern on a surface of the first insulating layer to connect one end of the first metal pattern to an exposed pad; 전체 구조 상부에 제 2 절연막을 도포하고, 상기 제 1 금속 패턴의 타단이 노출되도록 제 2 절연막의 해당 부분을 식각하는 단계;Applying a second insulating film over the entire structure, and etching a corresponding portion of the second insulating film to expose the other end of the first metal pattern; 전극이 상부를 향하게 배치된 캐패시터를 상기 패드 상부의 제 2 절연막 표면에 접착하고, 상기 전극이 노출되도록 캐패시터에 제 3 절연막을 도포하는 단계;Adhering a capacitor having an electrode facing upward to a surface of a second insulating film above the pad, and applying a third insulating film to the capacitor to expose the electrode; 상기 캐패시터의 전극과 제 1 금속 패턴의 타단을 제 2 금속 패턴으로 연결하는 단계;Connecting an electrode of the capacitor and the other end of the first metal pattern to a second metal pattern; 전체 구조 상부에 제 4 절연막을 도포하고, 상기 제 1 금속 패턴의 타단이 노출되어 볼 랜드가 형성되도록 상기 제 4 절연막의 해당 부분을 식각하는 단계;Applying a fourth insulating film over the entire structure, and etching a corresponding portion of the fourth insulating film so that the other end of the first metal pattern is exposed to form a ball land; 상기 볼 랜드에 솔더 페이스를 도포하고, 상기 솔더 페이스트에 솔더 볼을 마운트하는 단계; 및Applying a solder face to the ball land and mounting solder balls to the solder paste; And 상기 웨이퍼를 스크라이브 라인을 따라 절단하여, 개개의 반도체 칩으로 분리하는 단계를 포함하는 캐패시터 내장형 칩 사이즈 패키지 제조 방법.Cutting the wafer along a scribe line and separating the wafer into individual semiconductor chips.
KR10-1998-0059973A 1998-12-29 1998-12-29 Capacitor embedded chip size package and manufacturing method thereof KR100431307B1 (en)

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EP1182703A2 (en) * 2000-08-11 2002-02-27 Integrated Electronics & Packaging Technologies, Inc. Semiconductor device having integrated capacitor and/or inductor
WO2003065448A1 (en) * 2002-01-29 2003-08-07 Siemens Aktiengesellschaft Chip-size package with an integrated passive component
EP1359618A2 (en) * 2001-04-17 2003-11-05 Casio Computer Co., Ltd. Semiconductor device
KR100771146B1 (en) * 2006-11-30 2007-10-29 한국과학기술원 System in package using single layer capacitor
US9099313B2 (en) 2012-12-18 2015-08-04 SK Hynix Inc. Embedded package and method of manufacturing the same
FR3057993A1 (en) * 2016-10-25 2018-04-27 3Dis Technologies ELECTRONIC SYSTEM COMPRISING AN ELECTRONIC CHIP FORMING HOUSING AND METHOD OF MANUFACTURING
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EP1182703A2 (en) * 2000-08-11 2002-02-27 Integrated Electronics & Packaging Technologies, Inc. Semiconductor device having integrated capacitor and/or inductor
EP1182703A3 (en) * 2000-08-11 2005-09-28 Oki Electric Industry Company, Limited Semiconductor device having integrated capacitor and/or inductor
EP1359618A2 (en) * 2001-04-17 2003-11-05 Casio Computer Co., Ltd. Semiconductor device
EP1359618A3 (en) * 2001-04-17 2005-02-09 Casio Computer Co., Ltd. Semiconductor device
WO2003065448A1 (en) * 2002-01-29 2003-08-07 Siemens Aktiengesellschaft Chip-size package with an integrated passive component
KR100771146B1 (en) * 2006-11-30 2007-10-29 한국과학기술원 System in package using single layer capacitor
US9099313B2 (en) 2012-12-18 2015-08-04 SK Hynix Inc. Embedded package and method of manufacturing the same
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CN111029322A (en) * 2018-10-09 2020-04-17 南茂科技股份有限公司 Substrate structure and semiconductor package

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