CN111029322A - Substrate structure and semiconductor package - Google Patents

Substrate structure and semiconductor package Download PDF

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Publication number
CN111029322A
CN111029322A CN201910163106.6A CN201910163106A CN111029322A CN 111029322 A CN111029322 A CN 111029322A CN 201910163106 A CN201910163106 A CN 201910163106A CN 111029322 A CN111029322 A CN 111029322A
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China
Prior art keywords
chip
layer
patterned conductive
core layer
substrate structure
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Pending
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CN201910163106.6A
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Chinese (zh)
Inventor
刘志益
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication of CN111029322A publication Critical patent/CN111029322A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a substrate structure and a semiconductor package. The core layer includes a first surface. The first internal chip is disposed on the first surface of the core layer. The first circuit structure includes a first patterned conductive layer and a first conductive via. The first patterned conductive layer is disposed on the first surface of the core layer. The first conductive via is disposed on the first patterned conductive layer and electrically connected to the first internal chip. The first insulating layer covers the first surface of the core layer, the first internal chip, the first patterned conductive layer and part of the first conductive via, and exposes the upper surface of the first conductive via to form a first pad.

Description

Substrate structure and semiconductor package
Technical Field
The present invention relates to a substrate structure and a semiconductor package, and more particularly, to a substrate structure with an embedded chip and a semiconductor package.
Background
In order to achieve light, thin, short and small electronic product designs, semiconductor packaging technology is continuously advancing in an attempt to develop products that are smaller in size, lighter in weight, higher in integration degree and more competitive in the market. For example, techniques such as stacking chips on a substrate have been developed to meet the requirements of higher packaging density.
However, the processes of stacking chips on a substrate and packaging the stacked chips are complicated, which not only increases the packaging volume of the product, but also cannot expand the functionality of the product due to the limited space, so how to increase the number of chips in the limited space and further increase the packaging production efficiency is a challenge for those skilled in the art.
Disclosure of Invention
The invention provides a substrate structure and a semiconductor package, wherein a core layer is embedded with chips, so that the number of the chips which are arranged on the substrate structure and need to be packaged can be reduced.
The invention provides a substrate structure, which comprises a core layer, a first inner chip, a first circuit structure and a first insulating layer. The core layer includes a first surface. The first internal chip is disposed on the first surface of the core layer. The first circuit structure includes a first patterned conductive layer and a first conductive via. The first patterned conductive layer is disposed on the first surface of the core layer. The first conductive via is disposed on the first patterned conductive layer and electrically connected to the first internal chip. The first insulating layer covers the first surface of the core layer, the first internal chip, the first patterned conductive layer and part of the first conductive via, and exposes the upper surface of the first conductive via to form a first pad.
In an embodiment of the invention, the first internal chip has an active surface and an inactive surface opposite to each other. The inactive surface of the first inner chip faces the first surface of the core layer. The first patterned conductive layer extends from the active surface of the first inner chip to the first surface of the core layer.
In an embodiment of the invention, the substrate structure further includes a second circuit structure, a second insulating layer, and a second internal chip. The second circuit structure includes a second patterned conductive layer. The second patterned conductive layer is disposed on a second surface of the core layer, wherein the second surface is opposite to the first surface. The second insulating layer covers the second surface of the core layer and the second patterned conductive layer. The second circuit structure comprises a second conductive column penetrating through the second insulating layer and a second connecting pad connected to the second conductive column and exposed outside. The second conductive via is connected to the second patterned conductive layer. The second internal chip is disposed on the second surface of the core layer. The second patterned conductive layer is electrically connected to the second internal chip, and the second insulating layer covers the second internal chip.
In an embodiment of the invention, the substrate structure further includes a core layer via hole. The core layer via hole penetrates through the core layer and is electrically connected to the first patterned conductive layer and the second patterned conductive layer.
In an embodiment of the invention, the substrate structure further includes a third internal chip. The third internal chip is stacked on the first internal chip. The first patterned conductive layer is electrically connected to the third internal chip, and the first insulating layer covers the third internal chip.
In an embodiment of the invention, a size of the third internal chip is smaller than or equal to a size of the first internal chip.
In an embodiment of the invention, the third internal chip has an active surface and an inactive surface opposite to each other. The inactive surface of the third inner chip faces the first surface of the core layer, and the first patterned conductive layer extends from the active surface of the third inner chip to the first surface.
In an embodiment of the invention, the first internal chip is a passive device.
The invention provides a semiconductor package, which comprises the substrate structure and an external chip. The external chip is disposed on the first insulating layer and electrically connected to the first pad.
In an embodiment of the invention, the semiconductor package further includes a molding compound. The packaging colloid is configured on the first insulating layer and covers the external chip.
Based on the above, the substrate structure of the present invention can be used in a substrate factory to firstly dispose the first internal chip on the core layer of the substrate structure, and then connect the substrate structure with the first internal chip, which is manufactured in advance, with the external chip through the first conduction column in the substrate, so that compared with the conventional semiconductor package in which the chips are stacked on the substrate, the semiconductor package with the substrate structure of the present invention can reduce the number of chip layers to be packaged, reduce the number of chip stacking steps for stacking the chips on the substrate and packaging the stacked chips, further increase the package production efficiency, and increase the product storage capacity. In addition, the transmission distance and impedance of Input/output (I/O) can be effectively shortened, and the development of advanced products is facilitated.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a semiconductor package according to a third embodiment of the invention.
Description of the reference numerals
10. 20, 30: semiconductor package
100. 200 and 300: substrate structure
110: core layer
110 a: a first surface of the core layer
110 b: second surface of the core layer
111: core layer via hole
120: first internal chip
120a, 220a, 320 a: active surface
120b, 220b, 320 b: non-active surface
120 s: side wall
130: first circuit structure
131: first patterned conductive layer
132: the first conductive column
133: first pad
140: a first insulating layer
170: second circuit structure
171: second patterned conductive layer
172: the second conductive column
173: second pad
174: conductive terminal
180: a second insulating layer
190: external chip
191: packaging colloid
220: second internal chip
320: third internal chip
Detailed Description
Fig. 1 is a cross-sectional view of a semiconductor package 10 according to a first embodiment of the present invention. Please refer to fig. 1. The semiconductor package 10 of the present embodiment includes a substrate structure 100. The substrate structure 100 includes a core layer 110, a first internal chip 120, a first line structure 130, and a first insulating layer 140. In the substrate structure 100 of the present embodiment, the core layer 110 includes a first surface 110a and a second surface 110b opposite to the first surface 110 a. In some embodiments, the core layer 110 may be made of an insulating material with a relatively hard material, for example, the material of the core layer 110 is glass epoxy (FR-4).
In the substrate structure 100 of the present embodiment, the first internal chip 120 is disposed on the first surface 110a of the core layer 110. In other words, the first inner chip 120 is embedded in the substrate structure 100. In some embodiments, the first internal chip 120 may be a passive component, such as a resistor, a capacitor, an inductor, or the like, for example, but the invention is not limited thereto. In alternative embodiments, the first internal chip 120 may be an active device, such as a transistor, a memory, or the like, for example.
In the substrate structure 100 of the present embodiment, the first circuit structure 130 includes a first patterned conductive layer 131. The first patterned conductive layer 131 is disposed on the first surface 110a of the core layer 110. The material of the first patterned conductive layer 131 is, for example, copper.
In some embodiments, the first inner chip 120 has opposing active and inactive faces 120a, 120 b. The inactive surface 120b of the first inner chip 120 faces the first surface 110a of the core layer 110. The first patterned conductive layer 131 may extend from the active surface 120a of the first inner chip 120 to the first surface 110a of the core layer 110. In other words, the first patterned conductive layer 131 may extend from the active surface 120a of the first inner chip 120 to the first surface 110a of the core layer 110 along the sidewall 120s of the first inner chip 120.
In the substrate structure 100 of the present embodiment, the first insulating layer 140 covers the first surface 110a of the core layer 110, the first internal chip 120, and the first patterned conductive layer 131. The first insulating layer 140 has a through hole. The first circuit structure 130 further includes a first conductive via 132 and a first pad 133. The first conductive via 132 is disposed on the first patterned conductive layer 131 and formed in the through hole of the first insulating layer 140. The first insulating layer 140 covers a portion of the first conductive via 132, and an upper surface of the first conductive via 132 is exposed by the first insulating layer 140. The first pads 133 are formed on the upper surfaces of the first conductive vias 132 exposed by the first insulating layer 140. The first conductive via 132 is electrically connected to the first inner chip 120 through the first patterned conductive layer 131. The first pads 133 may include aluminum pads, copper pads, or other suitable metal pads. The material of the first conductive via 132 is, for example, copper, aluminum, nickel, gold, silver, tin, a combination thereof, or other suitable conductive material. The material of the first insulating layer 140 is, for example, green paint (solder mask), but the invention is not limited thereto.
In the substrate structure 100 of the present embodiment, a second circuit structure 170 is further included. The second line structure 170 includes a second patterned conductive layer 171. The second patterned conductive layer 171 is disposed on the second surface 110b of the core layer 110. In some embodiments, the material of the second patterned conductive layer 171 may be the same as or different from the material of the first patterned conductive layer 131, which is not limited in the present disclosure.
In the substrate structure 100 of the present embodiment, a second insulating layer 180 is further included. The second insulating layer 180 covers the second surface 110b of the core layer 110 and the second patterned conductive layer 171. The second insulating layer 180 has a through hole. The second circuit structure 170 further includes a second conductive via 172 and a second pad 173. The second conductive via 172 is disposed on the second patterned conductive layer 171 and formed in the through hole of the second insulating layer 180. In other words, the second conductive via 172 penetrates the second insulating layer 180. A portion of the second conductive via 172 is exposed by the second insulating layer 180. The second pads 173 are formed on the second conductive vias 172 exposed by the second insulating layer 180. That is, the second conductive via 172 connects the second patterned conductive layer 171 and the second pad 173. In some embodiments, the materials of the second insulating layer 180, the second conductive via 172 and the second pad 173 may be the same as or different from the materials of the first insulating layer 140, the first conductive via 132 and the first pad 133, respectively, which is not limited in the present invention.
In the substrate structure 100 of the present embodiment, a core layer via hole 111 is further included. The core layer via hole 111 penetrates the core layer 110 and is electrically connected to the first patterned conductive layer 131 and the second patterned conductive layer 171. The material of the core layer via 111 is, for example, copper, aluminum, nickel, gold, silver, tin, a combination thereof, or other suitable conductive material. In this manner, the substrate structure 100 is substantially completed.
The semiconductor package 10 of the present embodiment further includes an external chip 190 disposed on the substrate structure 100 having the first internal chip 120. More specifically, the external chip 190 is disposed on the first insulating layer 140 and electrically connected to the first pads 133. For example, the external chip 190 is electrically connected to the first pads 133 by wire bonding (wire bonding), for example. The external chip 190 may be the same as or different from the first internal chip 120, and the invention is not limited thereto.
The semiconductor package 10 of the present embodiment further includes a molding compound 191 disposed on the substrate structure 100 having the first internal chip 120. More specifically, the encapsulant 191 is disposed on the first insulating layer 140 and covers the external chip 190. In some embodiments, the semiconductor package 10 may further include conductive terminals 174. The conductive terminals 174 may be disposed on the second pads 173, and in the embodiment, the conductive terminals 174 are solder balls. In this way, the semiconductor package 10 is substantially completed.
In the semiconductor package 10 of the present embodiment, the first internal chip 120 may be electrically connected to an external circuit through the first patterned conductive layer 131, the core layer via hole 111, the second circuit structure 170 and the conductive terminal 174 corresponding to the first internal chip 120. The external chip 190 can be electrically connected to the first circuit structure 130 by wire bonding, and then electrically connected to the external circuit by the core layer via hole 111, the second circuit structure 170 and the conductive terminal 174 corresponding to the external chip 190.
The substrate structure of the invention can arrange the first internal chip on the core layer of the substrate structure in a substrate factory, and then connect the substrate structure with the first internal chip which is manufactured in advance with the external chip through the first conduction column in the substrate, therefore, compared with the traditional semiconductor package which stacks the chips on the substrate, the semiconductor package with the substrate structure of the invention can reduce the number of the chip layers which need to be packaged, reduce the process steps of stacking the chips on the substrate and packaging the stacked chips, further increase the package production benefit and improve the product storage capacity. In addition, the transmission distance and impedance of Input/output (I/O) can be effectively shortened, and the development of advanced products is facilitated.
Fig. 2 is a cross-sectional view of a semiconductor package 20 according to a second embodiment of the present invention. Referring to fig. 2, the semiconductor package 20 in fig. 2 is similar to the semiconductor package 10 in fig. 1, and therefore similar components are denoted by the same reference numerals, and detailed description thereof is omitted here. The semiconductor package 20 of fig. 2 differs from the semiconductor package 10 of fig. 1 in that: the substrate structure 200 in the semiconductor package 20 of fig. 2 further includes a second internal chip 220. The second inner chip 220 is disposed on the second surface 110b of the core layer 110. The second patterned conductive layer 171 is electrically connected to the second internal chip 220. The second insulating layer 180 covers the second internal chip 220. Based on design requirements, the type and size of the second internal chip 220 may be the same as or different from those of the first internal chip 120, so that the upper and lower surfaces of the core layer 110 of the substrate structure 200 are embedded with chips, which is not limited in the present invention.
In the substrate structure 200 of the present embodiment, the second internal chip 220 has an active surface 220a and an inactive surface 220b opposite to each other. The inactive surface 220b of the second inner chip 220 faces the second surface 110b of the core layer 110. The second patterned conductive layer 171 may extend from the active surface 220a of the second inner chip 220 to the second surface 110b of the core layer 110. In the substrate structure 200 of the present embodiment, the second internal chip 220 is disposed on the second surface 110b of the core layer 110, and thus, the number of chip stacks in the substrate structure can be further increased.
Fig. 3 is a cross-sectional view of a semiconductor package 30 according to a third embodiment of the present invention. Referring to fig. 3, the semiconductor package 30 in fig. 3 is similar to the semiconductor package 20 in fig. 2, and therefore similar components are denoted by the same reference numerals, and detailed description thereof is omitted here. The semiconductor package 30 of fig. 3 differs from the semiconductor package 20 of fig. 2 in that: the substrate structure 300 in the semiconductor package 30 of fig. 3 further includes a third internal chip 320. The third internal chip 320 is stacked on the first internal chip 120. The first patterned conductive layer 131 is electrically connected to the third inner chip 320 and the first inner chip 120, and the first insulating layer 140 covers the third inner chip 320. The third internal chip 320 may be the same as or different from the second internal chip 220 and the first internal chip 120 in terms of design requirements, and the invention is not limited thereto.
In some embodiments, the third inner chip 320 has opposing active and inactive faces 320a and 320 b. The inactive surface 320b of the third inner chip 320 faces the first surface 110a of the core layer 110. The first patterned conductive layer 131 extends from the active surface 320a of the third inner chip 320 to the first surface 110a of the core layer 110. In some embodiments, the size of the third internal chip 320 is smaller than or equal to the size of the first internal chip 120. In the substrate structure 300 of the present embodiment, the third internal chip 320 is disposed on the first surface 110a of the core layer 110, and thus, the number of chip stacks in the substrate structure can be further increased.
In summary, the substrate structure of the present invention can be used in a substrate factory to first dispose the first internal chip on the core layer of the substrate structure, and then connect the substrate structure with the first internal chip fabricated in advance with the external chip through the first conductive via in the substrate, so that compared with the conventional semiconductor package in which the chips are stacked on the substrate, the semiconductor package with the substrate structure of the present invention can reduce the number of chip layers to be packaged, reduce the number of chip stacking steps for stacking chips on the substrate and packaging the stacked chips, thereby increasing the package production efficiency and increasing the product storage capacity. In addition, the transmission distance and impedance of Input/output (I/O) can be effectively shortened, and the development of advanced products is facilitated.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A substrate structure, comprising:
a core layer comprising a first surface;
a first inner chip disposed on the first surface of the core layer;
a first circuit structure including a first patterned conductive layer and a first conductive via, wherein the first patterned conductive layer is disposed on the first surface of the core layer, and the first conductive via is disposed on the first patterned conductive layer and electrically connected to the first internal chip; and
the first insulating layer covers the first surface of the core layer, the first internal chip, the first patterned conductive layer and a part of the first conductive via, and exposes the upper surface of the first conductive via to form a first pad.
2. The substrate structure of claim 1, wherein the first inner chip has opposing active and inactive faces, the inactive face of the first inner chip facing the first surface of the core layer, the first patterned conductive layer extending from the active face of the first inner chip to the first surface of the core layer.
3. The substrate structure of claim 1, further comprising:
a second circuit structure comprising a second patterned conductive layer, wherein the second patterned conductive layer is disposed on a second surface of the core layer, wherein the second surface is opposite to the first surface;
a second insulating layer covering the second surface of the core layer and the second patterned conductive layer, wherein the second circuit structure includes a second conductive via penetrating through the second insulating layer and a second pad connected to the second conductive via and exposed outside, and the second conductive via is connected to the second patterned conductive layer; and
a second internal chip disposed on the second surface of the core layer, wherein the second patterned conductive layer is electrically connected to the second internal chip, and the second insulating layer covers the second internal chip.
4. The substrate structure of claim 3, further comprising:
a core layer via hole penetrating the core layer and electrically connected to the first patterned conductive layer and the second patterned conductive layer.
5. The substrate structure of claim 1, further comprising:
and a third internal chip stacked on the first internal chip, wherein the first patterned conductive layer is electrically connected to the third internal chip, and the first insulating layer covers the third internal chip.
6. The substrate structure of claim 5, wherein the third internal chip has a size less than or equal to the size of the first internal chip.
7. The substrate structure of claim 5, wherein the third inner chip has opposing active and inactive faces, the inactive face of the third inner chip facing the first surface of the core layer, the first patterned conductive layer extending from the active face to the first surface of the third inner chip.
8. The substrate structure of claim 1, wherein the first internal chip is a passive component.
9. A semiconductor package, comprising:
the substrate structure of any one of claims 1 to 8; and
an external chip disposed on the first insulating layer and electrically connected to the first pad.
10. The semiconductor package of claim 9, further comprising:
and the packaging colloid is configured on the first insulating layer and coats the external chip.
CN201910163106.6A 2018-10-09 2019-03-05 Substrate structure and semiconductor package Pending CN111029322A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107135651 2018-10-09
TW107135651A TW202015208A (en) 2018-10-09 2018-10-09 Substrate structure and semiconductor package

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Publication Number Publication Date
CN111029322A true CN111029322A (en) 2020-04-17

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043575A (en) * 1998-12-29 2000-07-15 김영환 Chip sized package having capacitor and fabrication method thereof
US20060022332A1 (en) * 2004-07-30 2006-02-02 Tetsuya Koyama Semiconductor chip-embedded substrate and method of manufacturing same
US20140167275A1 (en) * 2012-12-18 2014-06-19 SK Hynix Inc. Embedded package and method of manufacturing the same
CN104584701A (en) * 2012-06-22 2015-04-29 株式会社尼康 Substrate, imaging unit, and imaging device
US20150130000A1 (en) * 2013-11-12 2015-05-14 Teng Yen Lin Chip package structure and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043575A (en) * 1998-12-29 2000-07-15 김영환 Chip sized package having capacitor and fabrication method thereof
US20060022332A1 (en) * 2004-07-30 2006-02-02 Tetsuya Koyama Semiconductor chip-embedded substrate and method of manufacturing same
CN104584701A (en) * 2012-06-22 2015-04-29 株式会社尼康 Substrate, imaging unit, and imaging device
US20140167275A1 (en) * 2012-12-18 2014-06-19 SK Hynix Inc. Embedded package and method of manufacturing the same
US20150130000A1 (en) * 2013-11-12 2015-05-14 Teng Yen Lin Chip package structure and method for manufacturing the same

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Application publication date: 20200417