JPS56122219A - Automatic equalizer - Google Patents
Automatic equalizerInfo
- Publication number
- JPS56122219A JPS56122219A JP2478980A JP2478980A JPS56122219A JP S56122219 A JPS56122219 A JP S56122219A JP 2478980 A JP2478980 A JP 2478980A JP 2478980 A JP2478980 A JP 2478980A JP S56122219 A JPS56122219 A JP S56122219A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- pulse duration
- output
- error signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To increase the converging speed and the stability after convergence with no increment of the hard quantity for an FIA-type automatic equalizer, by controlling the amount of an integration in accordance with the size of the error signal. CONSTITUTION:The error signal ek delivered from the subtractor 5 is identified by the identifier 21 and then catches the code to produce sgnek. The delay line 6 with tap produces the signals sgnrk-N-sgnrkn, and these signals are multiplied by the signal sgnek at the multipliers 7-n...70...7N to produce the signal that shows a code (+ or -or o). On the other hand, the error signal ek is converted into a pulse duration signal through the level/pulse duration converting circuit 22. This pulse duration signal is applied to the AND circuit 230 and the NAND circuit 240 that are shown as the examples for the tap O, and then varies the width of the output signal of the multiplier 70. An integrator consisting of the diodes 250 and 260, the resistance 270, the amplifier 280 and the capacitor 290, each is actuated by the positive output pulse of the circuit 230 and the negative output pulse of the circuit 240. Thus a change is caused to the output of the integrator in accordance with the size of the signal ek.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2478980A JPS56122219A (en) | 1980-02-29 | 1980-02-29 | Automatic equalizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2478980A JPS56122219A (en) | 1980-02-29 | 1980-02-29 | Automatic equalizer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56122219A true JPS56122219A (en) | 1981-09-25 |
Family
ID=12147944
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2478980A Pending JPS56122219A (en) | 1980-02-29 | 1980-02-29 | Automatic equalizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56122219A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS617735A (en) * | 1984-06-22 | 1986-01-14 | Fujitsu Ltd | Equalizing mode controlling method of automatic equalizer |
-
1980
- 1980-02-29 JP JP2478980A patent/JPS56122219A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS617735A (en) * | 1984-06-22 | 1986-01-14 | Fujitsu Ltd | Equalizing mode controlling method of automatic equalizer |
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