JPS5611683A - Control system for refresh read-in write-in - Google Patents
Control system for refresh read-in write-inInfo
- Publication number
- JPS5611683A JPS5611683A JP8532979A JP8532979A JPS5611683A JP S5611683 A JPS5611683 A JP S5611683A JP 8532979 A JP8532979 A JP 8532979A JP 8532979 A JP8532979 A JP 8532979A JP S5611683 A JPS5611683 A JP S5611683A
- Authority
- JP
- Japan
- Prior art keywords
- address
- refresh
- write
- read
- fed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To enable the read-in and write-in even at refresh cycle, by detecting the agreement with the refresh address and the designated address and accessing the dynamic memory with the designated address. CONSTITUTION:At refresh cycle, the output of the refresh address counter RFAC is fed to the dynamic memory MEM via the multiplexer MPX1 controlled with the control circuit CNTL as the row address for refresh. In this case, when the read-in address is set to the address register ADRR2 from the input control unit IOC, the row address and the content of the counter RFAC are fed to the comparison circuit MAT and if they are in agreement, the agreement signal is fed to the circuit CNTL. Then, the address set to the register ADRR2 accesses the memory MEM via the multiplexer MPX1 and the read-in by the designated address is made. This is the same for the write-in and read-in and write-in can be made during the refresh cycle.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54085329A JPS5918792B2 (en) | 1979-07-05 | 1979-07-05 | Refresh read/write control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54085329A JPS5918792B2 (en) | 1979-07-05 | 1979-07-05 | Refresh read/write control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5611683A true JPS5611683A (en) | 1981-02-05 |
JPS5918792B2 JPS5918792B2 (en) | 1984-04-28 |
Family
ID=13855588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54085329A Expired JPS5918792B2 (en) | 1979-07-05 | 1979-07-05 | Refresh read/write control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5918792B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5295109A (en) * | 1991-06-21 | 1994-03-15 | Sharp Kabushiki Kaisha | Semiconductor memory |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202333U (en) * | 1985-06-07 | 1986-12-19 | ||
JPH0199897U (en) * | 1987-12-23 | 1989-07-04 |
-
1979
- 1979-07-05 JP JP54085329A patent/JPS5918792B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5295109A (en) * | 1991-06-21 | 1994-03-15 | Sharp Kabushiki Kaisha | Semiconductor memory |
Also Published As
Publication number | Publication date |
---|---|
JPS5918792B2 (en) | 1984-04-28 |
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