JPS5611682A - Matrix memory circuit using mis field effect transistor - Google Patents
Matrix memory circuit using mis field effect transistorInfo
- Publication number
- JPS5611682A JPS5611682A JP8731079A JP8731079A JPS5611682A JP S5611682 A JPS5611682 A JP S5611682A JP 8731079 A JP8731079 A JP 8731079A JP 8731079 A JP8731079 A JP 8731079A JP S5611682 A JPS5611682 A JP S5611682A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- memory circuit
- response
- write
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
Abstract
PURPOSE:To enable small sized circuit integration and to reduce the delay in response at write-in and readout, by constituting the current control circuit of the unit memory circuit forming the matrix memory circuit with two sets of parallel MISFETs. CONSTITUTION:The current control circuit D of the unit memory circuit Mij is formed with MISFETQ1, Q2 in parallel connection, they are conductive with the selection of the common row lines W1j, W2j, the current via FETQ1, Q2 is summed and fed to the current response circuit H and the information by the write-in as ROM is stored. Accordingly, the gate widths T1, T2 by the conductors 22, 23 of the lines W1j, W2j of FETQ1, Q2 are halved in comparison with the use of one FET, the resistance and capacitance is reduced, the time constant is reduced to about 1/4, and the reduction in response at write-in can be prevented. This is the same for the readout by the current application to one line W2j and the reduction in the response speed can be prevented. Further, with the constitution of reduced gate width, the circuit is small in size for circuit integration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54087310A JPS5849956B2 (en) | 1979-07-10 | 1979-07-10 | Matrix memory circuit using MIS field effect transistors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54087310A JPS5849956B2 (en) | 1979-07-10 | 1979-07-10 | Matrix memory circuit using MIS field effect transistors |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5611682A true JPS5611682A (en) | 1981-02-05 |
JPS5849956B2 JPS5849956B2 (en) | 1983-11-08 |
Family
ID=13911255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54087310A Expired JPS5849956B2 (en) | 1979-07-10 | 1979-07-10 | Matrix memory circuit using MIS field effect transistors |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5849956B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS583975A (en) * | 1981-06-29 | 1983-01-10 | Hitachi Ltd | Method and device for forming film by sputtering |
EP2444972A1 (en) * | 2009-06-15 | 2012-04-25 | Sony Corporation | Semiconductor device |
WO2023207236A1 (en) * | 2022-04-29 | 2023-11-02 | 华为技术有限公司 | Probability bit unit circuit, probability bit circuit system and control method therefor |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01177549U (en) * | 1988-05-26 | 1989-12-19 |
-
1979
- 1979-07-10 JP JP54087310A patent/JPS5849956B2/en not_active Expired
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS583975A (en) * | 1981-06-29 | 1983-01-10 | Hitachi Ltd | Method and device for forming film by sputtering |
JPH034620B2 (en) * | 1981-06-29 | 1991-01-23 | Hitachi Ltd | |
EP2444972A1 (en) * | 2009-06-15 | 2012-04-25 | Sony Corporation | Semiconductor device |
CN102460586A (en) * | 2009-06-15 | 2012-05-16 | 索尼公司 | Semiconductor device |
JPWO2010147029A1 (en) * | 2009-06-15 | 2012-12-06 | ソニー株式会社 | Semiconductor device |
EP2444972A4 (en) * | 2009-06-15 | 2014-03-19 | Sony Corp | Semiconductor device |
WO2023207236A1 (en) * | 2022-04-29 | 2023-11-02 | 华为技术有限公司 | Probability bit unit circuit, probability bit circuit system and control method therefor |
Also Published As
Publication number | Publication date |
---|---|
JPS5849956B2 (en) | 1983-11-08 |
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