GB1537114A - Memory apparatus - Google Patents

Memory apparatus

Info

Publication number
GB1537114A
GB1537114A GB3538176A GB3538176A GB1537114A GB 1537114 A GB1537114 A GB 1537114A GB 3538176 A GB3538176 A GB 3538176A GB 3538176 A GB3538176 A GB 3538176A GB 1537114 A GB1537114 A GB 1537114A
Authority
GB
United Kingdom
Prior art keywords
cell
volatile
memory
fets
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3538176A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP50104078A external-priority patent/JPS5228825A/en
Priority claimed from JP50104076A external-priority patent/JPS5228824A/en
Priority claimed from JP50156941A external-priority patent/JPS5279630A/en
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of GB1537114A publication Critical patent/GB1537114A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1537114 Non-volatile semi-conductor memory TOKYO SHIBAURA ELECTRIC CO Ltd 25 Aug 1976 [29 Aug 1975 (2) 25 Dec 1975] 35381/76 Heading H3T A memory comprises a plurality of memory cells, each cell having a power supply terminal, a volatile cell constituted by at least a pair of FETs 1, 2, with N (where N is greater than one) variable threshold FETs, M11-M1N, each connected between the power supply and one of the outputs of the volatile cell and N other variable threshold FETs, M21-M2N, connected likewise to the other output and the gates of these two sets connected to form N pairs each pair forming a non-volatile memory cell. The memory has digit lines D 1 , D 2 coupled to the memory cells and at least one memory selection line W selectively energized to select at least one memory cell and to permit data transfer to and from the volatile cell from the digit line. To transfer data from the volatile cell to a non-volatile cell, a positive pulse applied to a gate control line, MG2, say, puts both MNOSFETs 12, 22 in the high threshold state to erase any data stored in the respective cell M2, A subsequent negative pulse of, say, -30 V. on MG2 reads data into the cell as follows, one output of the volatile cell 1, 2 is at -15 V., the other at zero volts and so there will be 15 volts across one MNOSFET and 30 volts across the other, this last changes its threshold thereby storing non-volatilely the output Q or Q which was at 0 V. To subsequently read-out from the non-volatile cell M2 into the volatile cell the control line MGS is taken high and that on MGD low, this turns off FETs 3 and 4 and turns FET 7 on, thereby putting both Q and Q at -1À5 volt, i.e. lower than Vss by the threshold of 1, 2. Next a read-out voltage of -5 V. is applied to MG2 for the desired cell and MGD returned to a high level to turn FET 7 off. The potentials at Q, Q are now determined by the MNOSFETs 12, 22 and when subsequently MGS is taken low and FETs 3, 4 conduct then this state is maintained by the conduction of one of FET 1, 2.
GB3538176A 1975-08-29 1976-08-25 Memory apparatus Expired GB1537114A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP50104078A JPS5228825A (en) 1975-08-29 1975-08-29 Multiple memory unit
JP50104076A JPS5228824A (en) 1975-08-29 1975-08-29 Multiple storage unit
JP50156941A JPS5279630A (en) 1975-12-25 1975-12-25 Data processing unit

Publications (1)

Publication Number Publication Date
GB1537114A true GB1537114A (en) 1978-12-29

Family

ID=27310153

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3538176A Expired GB1537114A (en) 1975-08-29 1976-08-25 Memory apparatus

Country Status (2)

Country Link
DE (1) DE2638703C3 (en)
GB (1) GB1537114A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4168537A (en) * 1975-05-02 1979-09-18 Tokyo Shibaura Electric Co., Ltd. Nonvolatile memory system enabling nonvolatile data transfer during power on
US4202044A (en) * 1978-06-13 1980-05-06 International Business Machines Corporation Quaternary FET read only memory
US4263664A (en) * 1979-08-31 1981-04-21 Xicor, Inc. Nonvolatile static random access memory system
DE3821515A1 (en) * 1988-06-25 1989-12-28 Rico Mikroelektronik Gmbh Programmable gate arrangement

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676717A (en) * 1970-11-02 1972-07-11 Ncr Co Nonvolatile flip-flop memory cell

Also Published As

Publication number Publication date
DE2638703B2 (en) 1980-10-30
DE2638703C3 (en) 1981-07-16
DE2638703A1 (en) 1977-03-10

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Legal Events

Date Code Title Description
PS Patent sealed
746 Register noted 'licences of right' (sect. 46/1977)
PCNP Patent ceased through non-payment of renewal fee
PCPE Delete 'patent ceased' from journal

Free format text: NO.4909,PAGE 1074

PCNP Patent ceased through non-payment of renewal fee