JPS5677981A - Memory access circuit - Google Patents

Memory access circuit

Info

Publication number
JPS5677981A
JPS5677981A JP15304779A JP15304779A JPS5677981A JP S5677981 A JPS5677981 A JP S5677981A JP 15304779 A JP15304779 A JP 15304779A JP 15304779 A JP15304779 A JP 15304779A JP S5677981 A JPS5677981 A JP S5677981A
Authority
JP
Japan
Prior art keywords
current
signal line
word
nonselection
holding current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15304779A
Other languages
Japanese (ja)
Inventor
Masayuki Kano
Keiji Murasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP15304779A priority Critical patent/JPS5677981A/en
Publication of JPS5677981A publication Critical patent/JPS5677981A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To secure a high-speed access for a memory cell with a reduced amount of power consumption, by applying the voltage fluctuation according to the potential of the 2nd signal line to the base of a transistor of a current sink circuit and thus controlling the memory holding current. CONSTITUTION:The holding current control circuit 31 consisting of the resistances 42 and 43 is connected to the base of the transistor 40 in the current sink circuit 30. The memory holding current i1 turns to the function of the potential VWL of the 2nd signal line 11, and the memory holding current i145 turns to a major current in the word selection state under which a pair of word lines 10 and 11 have high potentials. While the current i1 becomes to a minor current in the nonselection state under which the lines 10 and 11 have low potentials. The fall time of the singal line 11 becomes slower than the fall time of the 1st signal line when the word selection changed to the word nonselection. Thus the discharge from the wiring capacity or the like can be absorbed in a short time to accelerate the transition. And a minor current is available during the nonselection state to reduce the amount of power consumption.
JP15304779A 1979-11-28 1979-11-28 Memory access circuit Pending JPS5677981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15304779A JPS5677981A (en) 1979-11-28 1979-11-28 Memory access circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15304779A JPS5677981A (en) 1979-11-28 1979-11-28 Memory access circuit

Publications (1)

Publication Number Publication Date
JPS5677981A true JPS5677981A (en) 1981-06-26

Family

ID=15553804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15304779A Pending JPS5677981A (en) 1979-11-28 1979-11-28 Memory access circuit

Country Status (1)

Country Link
JP (1) JPS5677981A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160895A (en) * 1984-11-09 1986-07-21 フエアチアイルド カメラ アンド インストルメント コ−ポレ−シヨン Apparatus and method for trapping memory cell power

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160895A (en) * 1984-11-09 1986-07-21 フエアチアイルド カメラ アンド インストルメント コ−ポレ−シヨン Apparatus and method for trapping memory cell power

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