JPS56108268A - Manufacture of non volatile semiconductor memory device - Google Patents
Manufacture of non volatile semiconductor memory deviceInfo
- Publication number
- JPS56108268A JPS56108268A JP1036280A JP1036280A JPS56108268A JP S56108268 A JPS56108268 A JP S56108268A JP 1036280 A JP1036280 A JP 1036280A JP 1036280 A JP1036280 A JP 1036280A JP S56108268 A JPS56108268 A JP S56108268A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- gate
- layer
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To improve write-erase characteristics of a non volatile semiconductor memory and stabilize its operation by forming the gate electrode provided on a non volatile semiconductor memory having a stacked-gate type MOS structure by empolying a two-layer structure comprising a floating gate electrode and a controlled- gate electrode. CONSTITUTION:On the periphery of the surface of a P type Si substrate 1 of surface index (100) or the like, a thick field SiO2 film 3 is formed, and the substrate 1 surrounded therewith is coated with a thin first gate SiO2 film 4. Then, a polycrystalline Si layer 5 to be a floating gate and a second gate SiO2 film 6 are grown being piled and extending over from the film 4 to the circumferential edge of the film 3, and N type impurity ions are implanted in order to provide the film 5 with conductivity. Then, a controlled-gate electrode 7 of polycrystalline Si is provided in the center of the film 6, and by using the electode 7 as a mask, the film 6, the layer 5 and the film 4 on both sides thereof are etched to remove. In the exposed substrate 1, an N type source region 8 and drain region 9 are formed by diffusion. Then, the electrode 7 is doped with an N type impurity to provide it with high conductivity. Thereby, the layer 5 and the electrode 7 provide an electrode having a two-layer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1036280A JPS56108268A (en) | 1980-01-31 | 1980-01-31 | Manufacture of non volatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1036280A JPS56108268A (en) | 1980-01-31 | 1980-01-31 | Manufacture of non volatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56108268A true JPS56108268A (en) | 1981-08-27 |
Family
ID=11748045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1036280A Pending JPS56108268A (en) | 1980-01-31 | 1980-01-31 | Manufacture of non volatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56108268A (en) |
-
1980
- 1980-01-31 JP JP1036280A patent/JPS56108268A/en active Pending
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