JPS56106421A - Constant ratio delay circuit - Google Patents

Constant ratio delay circuit

Info

Publication number
JPS56106421A
JPS56106421A JP834980A JP834980A JPS56106421A JP S56106421 A JPS56106421 A JP S56106421A JP 834980 A JP834980 A JP 834980A JP 834980 A JP834980 A JP 834980A JP S56106421 A JPS56106421 A JP S56106421A
Authority
JP
Japan
Prior art keywords
pulse train
clock
constant ratio
input
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP834980A
Other languages
English (en)
Other versions
JPH036694B2 (ja
Inventor
Takuji Sekiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Broadcasting Corp
Original Assignee
Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Japan Broadcasting Corp filed Critical Nippon Hoso Kyokai NHK
Priority to JP834980A priority Critical patent/JPS56106421A/ja
Priority to GB8101891A priority patent/GB2068156B/en
Priority to US06/227,740 priority patent/US4400666A/en
Priority to FR8101514A priority patent/FR2474796A1/fr
Priority to DE3102782A priority patent/DE3102782C2/de
Priority to DE3152878A priority patent/DE3152878C2/de
Publication of JPS56106421A publication Critical patent/JPS56106421A/ja
Publication of JPH036694B2 publication Critical patent/JPH036694B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
  • Television Signal Processing For Recording (AREA)
  • Digital Magnetic Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
JP834980A 1980-01-29 1980-01-29 Constant ratio delay circuit Granted JPS56106421A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP834980A JPS56106421A (en) 1980-01-29 1980-01-29 Constant ratio delay circuit
GB8101891A GB2068156B (en) 1980-01-29 1981-01-22 Delay circuit
US06/227,740 US4400666A (en) 1980-01-29 1981-01-23 Fixed rate delay circuit
FR8101514A FR2474796A1 (fr) 1980-01-29 1981-01-27 Circuit a retard de valeur fixe, applicable notamment a des multiplicateurs et des descriminateurs de frequences
DE3102782A DE3102782C2 (de) 1980-01-29 1981-01-28 Festratenverzögerungskreis mit einem Binarzähler
DE3152878A DE3152878C2 (de) 1980-01-29 1981-01-28 Schaltungsanordnung mit wenigstens zwei Festratenverzögerungskreisen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP834980A JPS56106421A (en) 1980-01-29 1980-01-29 Constant ratio delay circuit

Publications (2)

Publication Number Publication Date
JPS56106421A true JPS56106421A (en) 1981-08-24
JPH036694B2 JPH036694B2 (ja) 1991-01-30

Family

ID=11690739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP834980A Granted JPS56106421A (en) 1980-01-29 1980-01-29 Constant ratio delay circuit

Country Status (5)

Country Link
US (1) US4400666A (ja)
JP (1) JPS56106421A (ja)
DE (2) DE3152878C2 (ja)
FR (1) FR2474796A1 (ja)
GB (1) GB2068156B (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225640A (ja) * 1983-06-06 1984-12-18 Nitsuko Ltd クロツク位相同期方式
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
US4825109A (en) * 1986-06-13 1989-04-25 American Home Products Corporation Digital delay circuit
CH672066A5 (ja) * 1987-02-20 1989-10-31 Modima Sa
US4814879A (en) * 1987-08-07 1989-03-21 Rca Licensing Corporation Signal phase alignment circuitry
JP2611034B2 (ja) * 1990-07-10 1997-05-21 三菱電機株式会社 遅延回路
DE4238374B4 (de) * 1992-11-13 2005-11-10 Robert Bosch Gmbh Verfahren zur Erzeugung eines Signals mit einer steuerbaren stabilen Frequenz
JP2590741Y2 (ja) * 1993-10-18 1999-02-17 株式会社アドバンテスト 半導体試験装置用タイミング発生器
US5744992A (en) * 1995-12-20 1998-04-28 Vlsi Technology, Inc. Digital phase shifter
WO2008135305A1 (en) * 2007-05-08 2008-11-13 International Business Machines Corporation Method and apparatus for scalable and programmable delay compensation for real-time synchronization signals in a multiprocessor system with individual frequency control

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4896914U (ja) * 1972-02-18 1973-11-17
JPS50129209A (ja) * 1974-04-01 1975-10-13

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL234515A (ja) * 1957-12-24
US3137818A (en) * 1961-12-27 1964-06-16 Ibm Signal generator with external start pulse phase control
DE1219983B (de) * 1963-04-24 1966-06-30 Licentia Gmbh Schaltungsanordnung zur einstellbaren Verzoegerung eines Signals unter Verwendung eines Vorwaerts-Binaer-Zaehlers
FR1531117A (fr) * 1966-07-15 1968-06-28 Int Standard Electric Corp Déphaseur électronique bidirectionnel
US3562661A (en) * 1969-01-15 1971-02-09 Ibm Digital automatic phase and frequency control system
US3697879A (en) * 1971-08-31 1972-10-10 Eltee Pulsitron On-off pulse time control
DE2212911A1 (de) * 1972-03-17 1973-09-27 Sauter August Gmbh Verfahren zur frequenzvervielfachung
JPS5085320A (ja) * 1973-11-27 1975-07-09
US4016495A (en) * 1974-06-03 1977-04-05 The Wurlitzer Company Electronic musical instrument using plural programmable divider circuits
US4011517A (en) * 1975-01-22 1977-03-08 Stromberg-Carlson Corporation Timer apparatus for incrementing timing code at variable clock rates
DE2519722A1 (de) * 1975-05-02 1976-11-11 Licentia Gmbh Anordnung zum erzeugen eines vorimpulses zu jedem hauptimpuls einer impulsfolge
DE2520089A1 (de) * 1975-05-06 1976-11-18 Philips Patentverwaltung Schaltungsanordnung zur erzeugung aequidistanter von einem mechanischen taktgeber abgeleiteter elektrischer impulse
US4068179A (en) * 1976-05-17 1978-01-10 Design And Manufacturing Corporation Electronic cycle-select switching system
US4127823A (en) * 1977-02-23 1978-11-28 Frost R Jack Programmable controller
DE2928371C2 (de) * 1979-07-13 1982-07-01 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur Synchronisation von Zeitperioden zur Behandlung von Meßsignalen

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4896914U (ja) * 1972-02-18 1973-11-17
JPS50129209A (ja) * 1974-04-01 1975-10-13

Also Published As

Publication number Publication date
FR2474796A1 (fr) 1981-07-31
DE3102782A1 (de) 1982-01-28
GB2068156A (en) 1981-08-05
DE3102782C2 (de) 1983-10-27
GB2068156B (en) 1984-05-16
FR2474796B1 (ja) 1985-01-04
DE3152878C2 (de) 1985-07-04
JPH036694B2 (ja) 1991-01-30
US4400666A (en) 1983-08-23

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