JPS56105664A - Dynamic memory device - Google Patents

Dynamic memory device

Info

Publication number
JPS56105664A
JPS56105664A JP752480A JP752480A JPS56105664A JP S56105664 A JPS56105664 A JP S56105664A JP 752480 A JP752480 A JP 752480A JP 752480 A JP752480 A JP 752480A JP S56105664 A JPS56105664 A JP S56105664A
Authority
JP
Japan
Prior art keywords
layers
regions
type
substrate
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP752480A
Other languages
Japanese (ja)
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP752480A priority Critical patent/JPS56105664A/en
Priority to DE8181100424T priority patent/DE3173413D1/en
Priority to EP84114160A priority patent/EP0154685B1/en
Priority to EP81100424A priority patent/EP0033130B1/en
Priority to DE8484114160T priority patent/DE3177173D1/en
Priority to US06/227,936 priority patent/US4419682A/en
Publication of JPS56105664A publication Critical patent/JPS56105664A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To make capacities of digit lines small and also an area occupied by the lines small by a method wherein the digit linese constituting the memory device are piled on a capacitance unit of memory cells. CONSTITUTION:Concaves are selectively formed on the surface of a P<-> type Si substrate 11, being diffusion-formed with P<+> type regions 12 which are made an anti-reverse-rotation layer, the regions 12 are covered with thick SiO2 layers 14 which are made field oxide means, and thin SiO2 layers 14a are coverattached to the substrate 11 between the regions 12. Then, first polycrystalline Si layers 15 to be a capacitance are gaseous phase-grown on the whole surface, being perforated with a contact hole 30 for the digit lines, N<+> type regions 13 are formed corresponded to the layers 15 around the regions 12 and also, SiO2 films 18 are cover-attached on the layers 15. Thereafter, second polycrystalline Si layers 16 are formed which are located on the films 18 through the hole 30, in waveshape and made the digit lines, P type regions 31 of MOS elements for selecting addresses being formed in the substrate 11 where the layers 15 and 16 are absent, and third polycrystaline Si layers 20 for gates and an N<+> type layer 17 for wirings are formed.
JP752480A 1980-01-25 1980-01-25 Dynamic memory device Pending JPS56105664A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP752480A JPS56105664A (en) 1980-01-25 1980-01-25 Dynamic memory device
DE8181100424T DE3173413D1 (en) 1980-01-25 1981-01-21 Semiconductor memory device
EP84114160A EP0154685B1 (en) 1980-01-25 1981-01-21 Semiconductor memory device
EP81100424A EP0033130B1 (en) 1980-01-25 1981-01-21 Semiconductor memory device
DE8484114160T DE3177173D1 (en) 1980-01-25 1981-01-21 SEMICONDUCTOR STORAGE DEVICE.
US06/227,936 US4419682A (en) 1980-01-25 1981-01-23 Three level poly dynamic ram with poly bit lines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP752480A JPS56105664A (en) 1980-01-25 1980-01-25 Dynamic memory device

Publications (1)

Publication Number Publication Date
JPS56105664A true JPS56105664A (en) 1981-08-22

Family

ID=11668155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP752480A Pending JPS56105664A (en) 1980-01-25 1980-01-25 Dynamic memory device

Country Status (1)

Country Link
JP (1) JPS56105664A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6439058A (en) * 1987-08-04 1989-02-09 Mitsubishi Electric Corp Manufacture of semiconductor device
US4979013A (en) * 1986-03-13 1990-12-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979013A (en) * 1986-03-13 1990-12-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JPS6439058A (en) * 1987-08-04 1989-02-09 Mitsubishi Electric Corp Manufacture of semiconductor device

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