JPS56105540A - Adder - Google Patents

Adder

Info

Publication number
JPS56105540A
JPS56105540A JP688780A JP688780A JPS56105540A JP S56105540 A JPS56105540 A JP S56105540A JP 688780 A JP688780 A JP 688780A JP 688780 A JP688780 A JP 688780A JP S56105540 A JPS56105540 A JP S56105540A
Authority
JP
Japan
Prior art keywords
inputs
circuits
bytes
carry
byte
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP688780A
Other languages
English (en)
Inventor
Kanji Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP688780A priority Critical patent/JPS56105540A/ja
Publication of JPS56105540A publication Critical patent/JPS56105540A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP688780A 1980-01-25 1980-01-25 Adder Pending JPS56105540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP688780A JPS56105540A (en) 1980-01-25 1980-01-25 Adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP688780A JPS56105540A (en) 1980-01-25 1980-01-25 Adder

Publications (1)

Publication Number Publication Date
JPS56105540A true JPS56105540A (en) 1981-08-22

Family

ID=11650736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP688780A Pending JPS56105540A (en) 1980-01-25 1980-01-25 Adder

Country Status (1)

Country Link
JP (1) JPS56105540A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS622320A (ja) * 1985-06-27 1987-01-08 Nec Corp 加算回路
JPS622322A (ja) * 1985-06-27 1987-01-08 Nec Corp 加算回路
JPS62500474A (ja) * 1985-01-31 1987-02-26 バロ−ス・コ−ポレ−シヨン 高速ｂｃｄ／バイナリ加算器
JPS62111324A (ja) * 1985-06-27 1987-05-22 Nec Corp 加算回路
JPH03255525A (ja) * 1990-03-05 1991-11-14 Fujitsu Ltd 三入力加算回路
JPH04230519A (ja) * 1990-11-28 1992-08-19 Internatl Business Mach Corp <Ibm> ３オペランド演算論理機構におけるオーバーフローを決定する方法及び算術上のオーバーフローを検出する機構

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62500474A (ja) * 1985-01-31 1987-02-26 バロ−ス・コ−ポレ−シヨン 高速ｂｃｄ／バイナリ加算器
JPH0577095B2 (ja) * 1985-01-31 1993-10-26 Unisys Corp
JPS622320A (ja) * 1985-06-27 1987-01-08 Nec Corp 加算回路
JPS622322A (ja) * 1985-06-27 1987-01-08 Nec Corp 加算回路
JPS62111324A (ja) * 1985-06-27 1987-05-22 Nec Corp 加算回路
JPH0471215B2 (ja) * 1985-06-27 1992-11-13 Nippon Electric Co
JPH0471216B2 (ja) * 1985-06-27 1992-11-13 Nippon Electric Co
JPH03255525A (ja) * 1990-03-05 1991-11-14 Fujitsu Ltd 三入力加算回路
JPH04230519A (ja) * 1990-11-28 1992-08-19 Internatl Business Mach Corp <Ibm> ３オペランド演算論理機構におけるオーバーフローを決定する方法及び算術上のオーバーフローを検出する機構

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