JPS5596673A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5596673A
JPS5596673A JP362779A JP362779A JPS5596673A JP S5596673 A JPS5596673 A JP S5596673A JP 362779 A JP362779 A JP 362779A JP 362779 A JP362779 A JP 362779A JP S5596673 A JPS5596673 A JP S5596673A
Authority
JP
Japan
Prior art keywords
pad
conductivity
layer
film
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP362779A
Other languages
Japanese (ja)
Inventor
Tetsuji Yuasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP362779A priority Critical patent/JPS5596673A/en
Publication of JPS5596673A publication Critical patent/JPS5596673A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Element Separation (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To exactly avoid occurrence of short-circuit between the reverse conductivity type region and one conductivity semiconductor substrate by forming the reverse conductivity region surrounded by one conductivity insulation isolated layer and controlling the position of electrode or wire bonding pad when providing the pad through the insulating film on the reverse conductivity region.
CONSTITUTION: A reverse conductivity layer 3 is epitaxially grown on a one conductivity type semiconductor substrate 1, and two one conductivity layers 2' are diffused in predetermined region to thereby isolate the layer 3 in an island state. Then, a SiO2 film 4 is coated on the entire surface, an electrode or wire bonding pad 5 is formed on the film 4 while disposing in the inside the two layers 2', and the pad 5 is surrounded with a protecting film 6. Since only the layer 3 is formed udner the pad 5 according to this configuration, even if probes A, B are urged onto the pad 5 for specific inspection, there is no possibility of shorting between the pad 5 and the substrate 1. Thus, its reliability is improved, and this semiconductor device is adapted for automobiles or the like.
COPYRIGHT: (C)1980,JPO&Japio
JP362779A 1979-01-16 1979-01-16 Semiconductor device Pending JPS5596673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP362779A JPS5596673A (en) 1979-01-16 1979-01-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP362779A JPS5596673A (en) 1979-01-16 1979-01-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5596673A true JPS5596673A (en) 1980-07-23

Family

ID=11562726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP362779A Pending JPS5596673A (en) 1979-01-16 1979-01-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5596673A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04120230U (en) * 1991-04-08 1992-10-27 日本電気アイシーマイコンシステム株式会社 semiconductor equipment
US6107650A (en) * 1994-02-21 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04120230U (en) * 1991-04-08 1992-10-27 日本電気アイシーマイコンシステム株式会社 semiconductor equipment
US6107650A (en) * 1994-02-21 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and manufacturing method thereof
US6331466B1 (en) 1994-02-21 2001-12-18 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and manufacturing method thereof

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