JPS5593581A - Memory system - Google Patents

Memory system

Info

Publication number
JPS5593581A
JPS5593581A JP16523778A JP16523778A JPS5593581A JP S5593581 A JPS5593581 A JP S5593581A JP 16523778 A JP16523778 A JP 16523778A JP 16523778 A JP16523778 A JP 16523778A JP S5593581 A JPS5593581 A JP S5593581A
Authority
JP
Japan
Prior art keywords
address
banks
page
bank
detected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16523778A
Other languages
Japanese (ja)
Other versions
JPS5731232B2 (en
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16523778A priority Critical patent/JPS5593581A/en
Publication of JPS5593581A publication Critical patent/JPS5593581A/en
Publication of JPS5731232B2 publication Critical patent/JPS5731232B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To prevent extension of an object area of standby for a page fault time by selecting a prescribed address when page cross is detected.
CONSTITUTION: 2n-number banks BNK are interleaved in a memory unit correspondingly to lower n-number bits of logical address LA. The actual address obtained by converting a newly updated logical address is selected for the address of a bank where page cross is detected, and the actual address of address register group RALS which has not been updated yet is selected for other banks, and all banks are accessed simultaneously in respect to continuous data of an arbitrary length. Then, 2n-number page address bit counters for operations [+(2n-]1), -0], [+(2n -2), -1]...[+1, -(2n-2)], [+0, -(2n-1)] are provided correspondingly to 2n-number banks to detect page cross for every bank.
COPYRIGHT: (C)1980,JPO&Japio
JP16523778A 1978-12-31 1978-12-31 Memory system Granted JPS5593581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16523778A JPS5593581A (en) 1978-12-31 1978-12-31 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16523778A JPS5593581A (en) 1978-12-31 1978-12-31 Memory system

Publications (2)

Publication Number Publication Date
JPS5593581A true JPS5593581A (en) 1980-07-16
JPS5731232B2 JPS5731232B2 (en) 1982-07-03

Family

ID=15808458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16523778A Granted JPS5593581A (en) 1978-12-31 1978-12-31 Memory system

Country Status (1)

Country Link
JP (1) JPS5593581A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916323U (en) * 1982-07-22 1984-01-31 株式会社クボタ grass mower

Also Published As

Publication number Publication date
JPS5731232B2 (en) 1982-07-03

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