JPS5588448A - Discrete fourier converter - Google Patents

Discrete fourier converter

Info

Publication number
JPS5588448A
JPS5588448A JP16352178A JP16352178A JPS5588448A JP S5588448 A JPS5588448 A JP S5588448A JP 16352178 A JP16352178 A JP 16352178A JP 16352178 A JP16352178 A JP 16352178A JP S5588448 A JPS5588448 A JP S5588448A
Authority
JP
Japan
Prior art keywords
terms
multiplication
multipliers
discrete fourier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16352178A
Other languages
Japanese (ja)
Other versions
JPS6014386B2 (en
Inventor
Kiyohisa Wakabayashi
Fumio Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53163521A priority Critical patent/JPS6014386B2/en
Publication of JPS5588448A publication Critical patent/JPS5588448A/en
Publication of JPS6014386B2 publication Critical patent/JPS6014386B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details
    • H04J1/04—Frequency-transposition arrangements
    • H04J1/05—Frequency-transposition arrangements using digital techniques

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Complex Calculations (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To decrease the necessary multiplication number and the input addition number by giving previously the 2-point discrete Fourier conversion to the two input signals against a complex conjugate symmetric matrix element and then giving the real or imaginary number multiplication to the obtained real or imaginary number and furthermore with the 2-point discrete Fourier conversion given to the output. CONSTITUTION:The 2-point descrete Fourier conversion is given previously to a pair of inputs f1, f6, f2, f5 plus f3 and f4 which are multiplied by the complex conjugate multiplication term and through 2-point DFT circuits 11-13. Then the real numbers of real number terms Xn-X3n of the multiplication terms are multiplied addition terms of to the output of adder circuit 14 in circuits 11-13 each through multipliers 16-18, and imaginary number parts jYn-jYan of multiplication terms are multiplied through imaginary number multipliers 21-23 to the subtration term which received the subtraction via subtractor 15. Futhermore, the output of multipliers 16-18 are added together through adders 24 and 25, and input f0 is added via adder 26. This addition result is applied to DFT circuit 29 in the form of the 1st terms, and the outputs of multipliers 21-23 are added through adders 27 and 28. Thus the addition result of the 2nd term is obtained to be applied to circuit 29, and the 2-point discrete Fourier conversion is carried out through circuit 29.
JP53163521A 1978-12-25 1978-12-25 discrete fourier transformer Expired JPS6014386B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53163521A JPS6014386B2 (en) 1978-12-25 1978-12-25 discrete fourier transformer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53163521A JPS6014386B2 (en) 1978-12-25 1978-12-25 discrete fourier transformer

Publications (2)

Publication Number Publication Date
JPS5588448A true JPS5588448A (en) 1980-07-04
JPS6014386B2 JPS6014386B2 (en) 1985-04-12

Family

ID=15775440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53163521A Expired JPS6014386B2 (en) 1978-12-25 1978-12-25 discrete fourier transformer

Country Status (1)

Country Link
JP (1) JPS6014386B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7720897B2 (en) 2002-04-11 2010-05-18 Interdigital Technology Corporation Optimized discrete fourier transform method and apparatus using prime factor algorithm

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7720897B2 (en) 2002-04-11 2010-05-18 Interdigital Technology Corporation Optimized discrete fourier transform method and apparatus using prime factor algorithm

Also Published As

Publication number Publication date
JPS6014386B2 (en) 1985-04-12

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