JPS5588449A - Discrete fourier converter containing phase offset - Google Patents

Discrete fourier converter containing phase offset

Info

Publication number
JPS5588449A
JPS5588449A JP16352278A JP16352278A JPS5588449A JP S5588449 A JPS5588449 A JP S5588449A JP 16352278 A JP16352278 A JP 16352278A JP 16352278 A JP16352278 A JP 16352278A JP S5588449 A JPS5588449 A JP S5588449A
Authority
JP
Japan
Prior art keywords
addition
real
imaginary
output
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16352278A
Other languages
Japanese (ja)
Other versions
JPS6012673B2 (en
Inventor
Kiyohisa Wakabayashi
Fumio Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53163522A priority Critical patent/JPS6012673B2/en
Publication of JPS5588449A publication Critical patent/JPS5588449A/en
Publication of JPS6012673B2 publication Critical patent/JPS6012673B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details
    • H04J1/04—Frequency-transposition arrangements
    • H04J1/05—Frequency-transposition arrangements using digital techniques

Abstract

PURPOSE:To reduce the necessary multiplication number and the input addition number by giving the process to the real part of the complex input and the imaginary part via the real and imaginary signal processors each and then giving the addition and subtraction to both output through the post-process circuit with only the addition and subtraction to obtain the addition/subtraction output. CONSTITUTION:Real signal processor 16 carries out the basic conversion of RadixN including the phase offset which supplies each real part Xk<r> of N units of complex input signal and then delivers only the real part. In addition such processor 16, imaginary signal processor 17 is provided to carry out the basic conversion of RadixN containing the phase offset which supplies each imaginary part Xk<i> of the complex input signal and then delivers only the imaginary part. Then the outputs of processors 16 and 17 are applied to adder/subtractor circuit 19, and the NO.n output of processor 16 is defined as the imaginary part of NO.N-n. Then the No.n output of processor 17 is made to correspond to the real part of No.N-n. The addition and subtraction is given to each real and imaginary parts to give the operation to the output from No.0 to No.N, thus decreasing the necessary multiplication and input addition numbers each.
JP53163522A 1978-12-25 1978-12-25 Discrete Fourier Transformer with Phase Offset Expired JPS6012673B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53163522A JPS6012673B2 (en) 1978-12-25 1978-12-25 Discrete Fourier Transformer with Phase Offset

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53163522A JPS6012673B2 (en) 1978-12-25 1978-12-25 Discrete Fourier Transformer with Phase Offset

Publications (2)

Publication Number Publication Date
JPS5588449A true JPS5588449A (en) 1980-07-04
JPS6012673B2 JPS6012673B2 (en) 1985-04-02

Family

ID=15775460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53163522A Expired JPS6012673B2 (en) 1978-12-25 1978-12-25 Discrete Fourier Transformer with Phase Offset

Country Status (1)

Country Link
JP (1) JPS6012673B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111568A (en) * 1982-12-16 1984-06-27 Fujitsu Ltd Parallel four point fft circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111568A (en) * 1982-12-16 1984-06-27 Fujitsu Ltd Parallel four point fft circuit
JPH0219507B2 (en) * 1982-12-16 1990-05-02 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6012673B2 (en) 1985-04-02

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