JPS5588358A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS5588358A
JPS5588358A JP15986978A JP15986978A JPS5588358A JP S5588358 A JPS5588358 A JP S5588358A JP 15986978 A JP15986978 A JP 15986978A JP 15986978 A JP15986978 A JP 15986978A JP S5588358 A JPS5588358 A JP S5588358A
Authority
JP
Japan
Prior art keywords
resin
high heat
heat conductive
powder
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15986978A
Other languages
English (en)
Inventor
Yoshiaki Wakashima
Hideo Inayoshi
Kunihiko Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15986978A priority Critical patent/JPS5588358A/ja
Publication of JPS5588358A publication Critical patent/JPS5588358A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP15986978A 1978-12-27 1978-12-27 Resin-sealed semiconductor device Pending JPS5588358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15986978A JPS5588358A (en) 1978-12-27 1978-12-27 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15986978A JPS5588358A (en) 1978-12-27 1978-12-27 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS5588358A true JPS5588358A (en) 1980-07-04

Family

ID=15702983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15986978A Pending JPS5588358A (en) 1978-12-27 1978-12-27 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS5588358A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788583A (en) * 1986-07-25 1988-11-29 Fujitsu Limited Semiconductor device and method of producing semiconductor device
US5296740A (en) * 1991-03-20 1994-03-22 Fujitsu Limited Method and apparatus for a semiconductor device having a radiation part
US6239479B1 (en) * 1995-04-03 2001-05-29 Texas Instruments Incorporated Thermal neutron shielded integrated circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788583A (en) * 1986-07-25 1988-11-29 Fujitsu Limited Semiconductor device and method of producing semiconductor device
US5296740A (en) * 1991-03-20 1994-03-22 Fujitsu Limited Method and apparatus for a semiconductor device having a radiation part
US5424251A (en) * 1991-03-20 1995-06-13 Fujitsu Limited Method of producing semiconductor device having radiation part made of resin containing insulator powders
US6239479B1 (en) * 1995-04-03 2001-05-29 Texas Instruments Incorporated Thermal neutron shielded integrated circuits

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