JPS5585964A - Multi computer system - Google Patents

Multi computer system

Info

Publication number
JPS5585964A
JPS5585964A JP15955378A JP15955378A JPS5585964A JP S5585964 A JPS5585964 A JP S5585964A JP 15955378 A JP15955378 A JP 15955378A JP 15955378 A JP15955378 A JP 15955378A JP S5585964 A JPS5585964 A JP S5585964A
Authority
JP
Japan
Prior art keywords
unit
memory unit
μpc
computer system
rsr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15955378A
Other languages
Japanese (ja)
Other versions
JPS5833971B2 (en
Inventor
Minoru Ootsuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53159553A priority Critical patent/JPS5833971B2/en
Publication of JPS5585964A publication Critical patent/JPS5585964A/en
Publication of JPS5833971B2 publication Critical patent/JPS5833971B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To increase the processing ability of multi computer system, by constituting the memory unit possible for random access with the random shift register RSR and connecting the output of one RSR to the input of another RSR.
CONSTITUTION: One serial output SO of the memory unit consisting of RSR15-1, 15-2 and another serial input SI are connected with the copy buses 18-1, 18-2. In transfering the content of the memory unit 15-1 at μPC 17-1 to the memory unit 15-2 at μPC 17-2, the content of the unit 15-1 is sequentially transferred to the unit 15-2 via the bus 18-1 by taking the logic of the control input C of the unit 15-2 as 0. During the period of data transfer, the μPC 17-1 can access the memory unit freely via the bus 16-1. The transfer of the content of the unit 15-2 to the unit 15-1 is similarly made by taking the logic of the control input of the unit 15-1 as 0. Accordingly, the data transfer outside the computer system and the access in the system can simultaneously be made.
COPYRIGHT: (C)1980,JPO&Japio
JP53159553A 1978-12-21 1978-12-21 multi computer system Expired JPS5833971B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53159553A JPS5833971B2 (en) 1978-12-21 1978-12-21 multi computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53159553A JPS5833971B2 (en) 1978-12-21 1978-12-21 multi computer system

Publications (2)

Publication Number Publication Date
JPS5585964A true JPS5585964A (en) 1980-06-28
JPS5833971B2 JPS5833971B2 (en) 1983-07-23

Family

ID=15696248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53159553A Expired JPS5833971B2 (en) 1978-12-21 1978-12-21 multi computer system

Country Status (1)

Country Link
JP (1) JPS5833971B2 (en)

Also Published As

Publication number Publication date
JPS5833971B2 (en) 1983-07-23

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