JPS5833971B2 - multi computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-computer system in which a processor can freely access a storage device even during a period in which data is transferred from one computer system to another.

In a multi-computer system that has multiple computer systems, when data is transferred from the storage device of one computer system to the storage device of another computer system using the north method, the data bus and address bus are exclusively used for DMA. , the processor cannot access the storage device.

In order to maximize the processing power of the entire multi-computer system, it is desirable that the processor be able to access its own storage device even during data transfer.

The present invention is based on the above considerations, and provides a multi-computer system in which a processor can access its own storage device even during a period when data is being transferred from one computer system to another. The purpose is to provide a system.

Therefore, the multi-computing system of the present invention includes at least two computer systems each having a processing unit, a bus, and a randomly accessible storage device connected to the bus.
In a multi-computer system with multiple computers, the randomly accessible storage device in each computer is connected to multiple flip-flops and multiple access gates provided between adjacent flip-flops. When the random data human output line and the control (property) human power have a predetermined value, the data output from the serial output terminal is input to the first stage flip-flop, and the said side (property) human power has a predetermined value. a shift register having an input selection means for inputting data input manually from a serial input terminal to a first-stage flip-flop; an address counter whose contents are updated in synchronization with the shift operation of the shift register; and access gate control means for supplying a read designation signal or a write designation signal to one of the plurality of access gates based on the contents of the address counter, the designated address, and the external signal. The serial output terminal of the random shift register in one computer system is connected to the random shift register in the other computer system.
It is characterized in that it is connected to the serial input terminal of the shift register through a signal line.

Hereinafter, the present invention will be explained with reference to the drawings.

In Figures 1 and 2, 1 is a shift register, 2 is a decoder, 3 is a subtracter, 4 is an address counter, 5 and 6
is an AND circuit, T and 8 are OR circuits, 9 and 10 are NAN gates, 11 and 12 are NOT circuits, 13 and 14 are tri-state gates, FFo to FFn-1 are RS flip gates.
Flop, Go or Gn□ is access gate, lo
1 to 1 are access gate control lines, Ri is a read designation line for flip-flop FFi, Wl-1 is a write designation line for flip-flop FF1-1,
C represents a control input, SI represents a serial input, SO represents a serial output, and D represents a random data output.

The random shift register of FIG. 1 operates as follows.

Now, time t. In (a) the content of the address counter is 0''.

(→ Bit B.

+B1...Bn-1 are stored in flip-flops FFo, FF1...FF,1, respectively.

(c) beep) B.

, B1...Bn-1 respectively at the 0th address and the 1st address.
...The n-th address is assigned.

Assume that

Under the above assumption and provided that no data is written, when i clocks are input to the random shift register, the contents of address counter 4 will be i'''
Therefore, bit Bo at address 0 is flip-flop F.
F,i, and the bit Bj at the jth address is flipped.
Stored in flop FF.

That is, when the content of address counter 4 is "i", the jth
First bit Bj′f! ! : When reading, it is sufficient to read the contents of the flip-flop FFn-1-j, and the j-th
If it is desired to change the logical value of bit BJ of an address, the contents of flip-flop FF, i7j may be changed.

The subtracter 3 calculates the difference between the contents of the address counter 4 and the specified address, and the decoder 2 uses the subtracter 3 described above.
One access gate control line 'n
-1-j is selected.

When control input C is logic "0", data circulates through shift register 1.

2nd access gate Gi (access i=0゜■・
... n-1) is a block diagram.

Wi□ indicates a write designation line for the flip-flop FF1-1 and a read designation line from the R1-th flip-flop FFi.

Note that the access gate signal line Ai is connected to the designated lines Rt, W
i-1.

If the read/write signal W specifies reading while the chip select signal C8 specifies random access, only the specified line Ri becomes logic "0" and the tristate gate 14 opens. If the read/write signal W specifies write, only the designated line VVi-1 becomes logic "0"
As a result, Tri-State Gate 13 opens.

For example, when the content of the flip-flop FFi is logic "1" and the designated line R1 becomes logic rOJ, a logic "0" is output from the inverted output of the flip-flop FFi, which passes through the OR circuit 8 and the NAND circuit 10. is inverted with
Random data is output from the input/output through tristate gate 14.

For example, flip-flop designation line Wi, -1 is logic "0" and random data input/output is logic "0".
When the logic [l] is supplied, the OR circuit 8 outputs the logic [l],
NAN circuit 9 is logic rOJ, NAND circuit 10 is logic r
lJ' is output, and the logic "l" is input to the flip-flop FFi.

For details of the above-mentioned random shift register, please refer to Japanese Patent Application No. 158659/1986 (!
027 Publication).

FIG. 3 is a block diagram of one embodiment of the present invention.
15-1 and 15-2 are storage devices composed of random shift registers, 16-1 and 16-2 are buses, and 17-1
and 17-2 are microprocessors, 18-1 and 18-2
indicate signal lines, respectively.

Needless to say, the random shift register constituting the storage device 15-115-2 has the configuration as explained in FIGS. 1 and 2.

The signal line 18-1 connects the serial output SO of the random shift register 15-1 and the random shift register 15-1.
The signal line 18-2 connects the serial output SO of the random shift register 15-2 and the serial input SL of the random shift register 1s-i.

A data bus within bus 16-1 connects the data output of microprocessor 17-1 and a random data input/output of storage device 15-1, and an address bus within bus 16-1 connects the data output of microprocessor 17-1 with the random data input/output of storage device 15-1. The address terminal of the processor 17-1 and the designated address of the storage device 15-1 are connected.

Bus 16-2 connects microprocessor 17-2 and storage device 15-2 in the same manner as bus 16-1.

The contents of the storage device 15-1 on the microprocessor 11-1 side are transferred to the storage device 15 on the microprocessor 17-2 side (7).
-2, the control manual C of the storage device 152 may be set to logic "O".

If the control input (J logic is 10J), the contents of the storage device 15-1 are sequentially transferred to the storage device 15-2 via the signal line 1s-ii.

Even during this data transfer period, the microprocessor 1T-1 can freely access its own storage device 15-1 via the bus 16-1.

The same applies to the microprocessor 17-2.

When data is transferred from the storage device 15-2 to the storage device 15-1, logic "O" may be set to the control input C' of the storage device 15-1.

As is clear from the above description, according to the present invention, a random shift register is used as a storage device of a computer system, and the serial output terminal of the random shift register of one computer system is connected to the serial output terminal of the random shift register of the other computer system.
Connect to the serial input terminal of the shift register with a signal line,
Because data is transferred from one computer system to another without using the data bus and address bus, each computer system uses the data bus and address terminals even during data transfer. It can be used to access the own random shift register.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a random shift register used in the present invention, FIG. 2 is a block diagram of an access gate, and FIG. 3 is a block diagram of one embodiment of the present invention. 1...Shift register, 2...Decoder, 3...Subtractor, 4...Address
Kawanta, 5 and 6...AND circuit, 7 and 8...
・OR circuit, 9 and 10...NAND AND circuit and 12...NOT circuit, 13 and 14...
Tri-state gate, 15-1 and 15-2...
・Storage device composed of random shift registers,
16-1 and 16-2... bus, 17-1 and 17
-2...Microprocessor, 18-1 and 18
-2...Signal line, FFo or FF, 1...
...RS flip-flop, Go or Gn,...
...access gate, l. Or l. -1・・・Access gate system (Foundation)
line, Ri is a read designation line for flip-flop FFi, W, -1...Flip-flop FF,
Write designation line for 1, C... Control input, S
I...Serial human power, SO...Serial output, D...Random data input/output.

Claims (1)

[Claims] 1. In a multi-computer system having at least two computer systems each having a processing unit, a bus, and a randomly accessible storage device connected to the bus, the randomly accessible storage device in each computer is connected to a plurality of randomly accessible storage devices. A plurality of access gates provided between a flip-flop and an adjacent flip-flop, random data input/output lines connected to each access gate, and a serial output terminal when the control input has a proprietary value. A shift register having manual selection means for inputting output data to a first-stage flip-flop and inputting data input from a serial input terminal to the first-stage flip-flop when the control input has another predetermined value. - An address counter whose contents are updated in synchronization with the shift operation of the shift register, and one of the plurality of access gates based on the contents of the address counter, the specified address, and the external control signal. A random shift register is provided with an access gate control means for supplying a read designation signal or a write designation signal to the random shift register, and the serial output terminal of the random shift register in one computer system is connected to the random shift register in the other computer system. A multi-computer system characterized by connecting a serial input terminal of a register with a signal line.