經濟部中央標準局員工消費合作社印製 321723 A7 ---- B7 五、發明説明（】） 發明之領域 本發明關於積體電路，及特指一測試及診斷機構以使用 在包括一精簡指令集計算（RISC)中央處理器（CPU>9積體電 路’其係被用在攜帶式設備及結合一晶片上記憶體區塊可 被使用做一窖藏器或隨機存取記憶體。 發明之背景 攜帶式設備包括電子儀器諸如個人資訊管理器，分格式 電話’數位攝影器，手持遊樂器，條碼掃描器，醫療設備 ’電子儀器及導航系統，特別是全球定位衛星導航系統。 爲獲致商業成功’攜帶式設備需要低成本積體電路，具 低功率需求以確保長久電池壽命，及具有高標準性能以確 保輸出之精確和可用。此外，該積體電路和攜帶式設備其 他元件間之該界面必須是一種插放式設計以使得一單型式 積體電路可使用在多個攜帶式設備。部份彈性是該攜帶式 設備設計者必須可簡單地結合該積體電路進入該等設備以 爲一現成組件，其不需要任何内部改良以使用在多種應用 〇 該等積體電路中央處理器之"計算能力"，如英代爾 3 0 * 8 6及奔騰系列晶片，和摩托羅拉68〇〇〇系列晶片，在過 去幾年顯著地增加。同時，該等晶片的尺寸隨著其功率需 求而明顯成長。該等晶片被設計爲繁複指令集計算（CISC) 及需要關聯隨機存取記憶體（RAM)顯著的區塊於該等運用 已被寫入以執行包含該等已成長晶片之電腦，似乎並無限 制，需要大量硬碟空間，該等繁複指令集計算設備在攜帶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------f 袈 II (請先閱讀背面之注意事項再填寫本頁) -訂 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（2 ) 式設備由於其功率需求和尺寸並不容易使用。 精簡指令集計算（RISC)原本是使用在高階圖形應用，及 在電腦輔助工程/電腦輔助設計（CAE/CAD)工作站。該精簡 指令集计算架構，無論如何，致使一積體電路具有明顯較 小晶粒尺寸，因爲該精簡指令集計算技術的較小指令組需 要較少電晶體以運作，此導致較簡單設計，結果需要較少 時間來完成及除錯。此外，較小晶片具有較短訊號路徑表 不每一指令週期是一較短期間。該精簡指令集計算中央處 理機的相對尺寸相較於一繁複指令集計算中央處理機是明 顯地較小，該英代爾386 SL晶片約是17〇1111112,而一具相似 計算能力的精簡指令集計算則約大5 mm2。 泫較小尺寸精簡指令集計算基礎中央處理機使得該精簡 指令集計算架構非常適合於系統上晶片（s〇c)應用，其中該 中央處理機及多個其他架構被置於一單晶片上。該一系統 上晶片可導致一遠小於複雜指令集計算中央處理機之晶片 ’但其包含所有計算和控制架構在一單積體電路上。一系 統上架構一般包括該精簡指令集計算和某些型式局部隨機 存取記憶體及/或資料窖藏器。此外，該晶片可包括内部和 外部匯流排控制器，不同型式通訊埠，一中斷控制器，及 脈衝寬度調制器，不同組態暫存器，不同計時器/計數器結 構及些型式輸出fe制器，如一液晶顯示器控制器。該 一結構可被組態爲一32數元架構，與關聯週邊設備集成入 該晶片，該集成容許攜帶式設備設計者結合該晶片以減少 開發週期和加速產品上市。該晶片結構可具有一外部16數 (請先閲讀背面之注意事項再填寫本頁) 袈.Printed 321723 A7 ---- B7 by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (】) Field of the invention The present invention relates to integrated circuits and specifically refers to a testing and diagnostic institution for use in including a streamlined instruction set Computing (RISC) central processing unit (CPU> 9 integrated circuit ”which is used in portable devices and combined with an on-chip memory block can be used as a cellar or random access memory. BACKGROUND OF THE INVENTION Devices include electronic instruments such as personal information managers, sub-format phones 'digital cameras, handheld game instruments, bar code scanners, medical devices' electronic instruments and navigation systems, especially global positioning satellite navigation systems. For commercial success It requires low-cost integrated circuits, low power requirements to ensure long battery life, and high standard performance to ensure accurate and usable output. In addition, the interface between the integrated circuit and other components of portable devices must be A plug-in design so that a single-type integrated circuit can be used in multiple portable devices. Part of the flexibility is that Designers of portable devices must simply integrate the integrated circuit into these devices as a ready-made component, which does not require any internal improvements to be used in a variety of applications. The "computing power" of the integrated circuit central processor , Such as Intel 3 0 * 8 6 and Pentium series chips, and Motorola 68000 series chips, have increased significantly in the past few years. At the same time, the size of these chips has grown significantly with their power requirements. The chip is designed as a complex instruction set calculation (CISC) and a significant block that requires associative random access memory (RAM) has been written in these applications to execute the computer containing these grown chips, there seems to be no limit, A lot of hard disk space is required, and these complicated instruction set computing devices carry this paper. The standard of the Chinese National Standard (CNS) A4 (210X297 mm) is applicable --------- f 袈 II (Please read the back of the first (Notes and then fill out this page)-Order A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (2) The device is not easy to use due to its power requirements and size. Instruction set computing (RISC) was originally used in high-end graphics applications and in computer-aided engineering / computer-aided design (CAE / CAD) workstations. The simplified instruction set computing architecture, no matter what, results in an integrated circuit with significantly smaller crystals Grain size, because the smaller instruction set of the reduced instruction set calculation technology requires fewer transistors to operate, which results in a simpler design, which results in less time to complete and debug. In addition, smaller chips have shorter signal paths Each instruction cycle is a shorter period. The relative size of the reduced instruction set computing central processing unit is significantly smaller than that of a complicated instruction set computing central processing unit, and the Intel 386 SL chip is about 17 〇1111112, and a reduced instruction set with similar computing power is about 5 mm2 larger. The smaller size of the reduced instruction set computing basic central processing unit makes the reduced instruction set computing architecture very suitable for system on chip (SOC) applications, where the central processing unit and multiple other architectures are placed on a single chip. This system-on-chip can result in a chip that is much smaller than a complex instruction set computing central processor, but it contains all the computing and control architecture on a single integrated circuit. A system architecture generally includes the reduced instruction set calculation and some types of local random access memory and / or data storage. In addition, the chip can include internal and external bus controllers, different types of communication ports, an interrupt controller, and pulse width modulator, different configuration registers, different timer / counter structures, and some types of output controllers , Such as an LCD controller. The structure can be configured as a 32-bit architecture integrated with associated peripheral devices into the chip. The integration allows portable device designers to integrate the chip to reduce development cycles and accelerate time-to-market. The chip structure can have an external 16-digit number (please read the precautions on the back before filling this page).
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本紙張尺度適用中國國家標準（CNS 公釐) Α7 32ί723 ------ Β7_ 五、發明説明（3 ) 元資料匯流排與一積體和可程式化匯流排控制器可支揮8 或16數元靜態隨機存取記憶體，動態隨機存取記憶體，可 抹除可規劃唯讀記憶體及/或記憶體設備，其不需要其他缓 衝器以與該積體電路作用。該晶片可操作在3 3伏特或5伏 特，各別需要100毫瓦至350毫瓦。 經由結合多個週邊設備在該晶片上，及提供一内部匯流 排在該中央處理機和週邊設備内，其可導引多個作動在晶 片上，且同時控制非晶片操作，如記憶體儲存和檢索。 該積體電路可包括一記憶體界面以提供多個可程式化晶 片致能。容許使用者設定等待狀態及記憶體寬度，8或16 數元寬。該積體電路提供位址解碼和動態隨機存取記憶體 控制邏輯，其容許一外部匯流排主控器以執行資料傳送而 無需外部位址解碼或外部動態隨機存取記憶體控制器。在 該例其中順序存取被使用，該積體電路由外部供給自動地 増加，匯流主導器供給的初始記憶體位址，因而加速傳送 〇 本發明之此應用是一測試和診斷機構其包括一外部匯流 排主控控制器，及其容許虛擬地存取所有積體電路上的内 部暫存器，及其容許該晶片上靜態随機存取記憶體/動態随 機存取記憶體控制器以存取外部記憶體。 本發明的該等和其他目的和優點將隨著敘述及附圖之説 明而更加完全明顯。 附圖之簡單説明 圖1是本發明系統上晶片結構的一方塊圖； ____ -6- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ~ II I "-----—f (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 _ B7 I":發明説明ΰ ) ' - 圖2是本發明該積體電路和連接至此該非晶片上設備間之 接腳連接的一方塊圖。 Μ佳具體例的詳細説明 首先參閲圖1，本發明的一系統上晶片結構一般被描述述 爲10。積體電路10包括一 32數元精簡指令集計算中央處 理機12被連接至一 32數元内部匯流排14。中央處理機I] 被直接連接至内部匯流排控制器16，其依序被連接至匯流 排14及至一匯流排映圖18。積體電路1〇另包括一局部隨 機存取記憶體（靜態隨機存取記憶體）2〇，一結合指令/資料 窖藏器22，及一外部存取埠24。在該較佳實施例，積趙電 路1 0企圖連接至一液晶顯示（LCD)及至該終端，包括一液 晶顯示控制器以被連接至一液晶顯示面板界面28。一外部 匯流排控制器30被提供及被連接至一 26數元外部記憶體界 面3 2及外部晶片選擇3 4。 多個組態暫存器3 6被提供，其功能將隨後予以描述。在 該較佳實施例，組態暫存器3 6係位於内部匯流排控制器1 6 内。多個内部"周邊設備"位於積體電路1 〇上，及被連接至 内部匯泥排1 4，及包括一萬向非同步收.發記號（UART) 38 ，一平行埠40, 一計時器/計數器42, 一中斷控制器44， 及一脈寬調制器（PWM) 46。 一外部匯流排主控器48，也在此參閲如一外部設備，被 連接至外部記憶體界面32，外部晶片選擇34及至一外部記 憶體5 0。外部記憶體5 0可包括靜態隨機存取記憶體和動態 随機存取記憶體埠至此。週邊設備，標示爲5 2，被連接至 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） tn · I {装-- {請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5 ) 外部記憶趙界面3 2及外部晶片選擇3 4。外部記憶髏界面 3 2及外部晶片選擇3 4是，在該較佳實施例，外部匯流排控 制器3 0的一部份。該等熟悉本技藝者將辨識參考數字丨2至 46之物件形成積體電路10的組件，而參考號碼大於46之 物件則爲非晶片上設備。 在該較佳實施例，積體電路10被構造成一 160接腳薄四 排平裝（TQFP)组件。現參閲圖2，對本發明特別有興趣者 將發現該等接腳被連接至外部匯流排主控器48及是特定匯 流排主控需求（BREQ)用以傳送一需求訊號，匯流排主控器 授予（BGR)用以傳送一授與訊號，傳送需求（xrEq)，及傳 送確認（XACK)。訊號流係由箭頭線連接積體電路1 〇所表示 ，外部匯流排主控器4 8，動態随機存取記憶體5〇生，靜態 随機存取記憶體5 及週邊設備5 2。較佳係該外部記憶體 界面3 2和外部晶片選擇3 4係實質地位於較佳實施例的外部 匯流排控制器30内。接腳匯流排主控需求及傳送需求被關 聯至此爲一需求機構，當接腳匯流排主控授與和傳送確認 則當做是一授與機構。資料及/或指令將接著流通於積體電 路1 0和外部記憶體匯流排上週邊設備以爲資料，位址和控 制功能集體標示如匯流排5 4。 爲便詳細描述前述，現請參閲圖1和圖2，中央處理機12 容許外邵匯流排主控器4 8控制外部記憶體界面3 2和使用晶 片上靜態隨機存取記憶體/動態隨機存取記憶體控制器，一 般位於内部匯流排控制器j 6内，以傳送資料。前面確定之 四種訊號使用於元成外部界面3 2控制。應瞭解外部匯流排 本紙張尺度適用中國國豕標準（CNS ) A4規格（210x297公髮；） ---------策— - ' (請先閲讀背面之注意事項再填寫本頁)This paper scale is applicable to the Chinese National Standard (CNS mm) Α7 32ί723 ------ Β7_ V. Invention description (3) Metadata bus and an integrated body and programmable bus controller can support 8 or 16 The digital static random access memory and the dynamic random access memory can be erased and can be programmed with read-only memory and / or memory devices, which do not require other buffers to interact with the integrated circuit. The wafer can be operated at 33 volts or 5 volts, each requiring 100 to 350 milliwatts. By combining multiple peripheral devices on the chip and providing an internal bus in the central processing unit and peripheral devices, it can guide multiple actions on the chip and simultaneously control non-chip operations, such as memory storage and Search. The integrated circuit may include a memory interface to provide multiple programmable wafer enablement. Allow users to set the waiting status and memory width, 8 or 16 digits wide. The integrated circuit provides address decoding and dynamic random access memory control logic, which allows an external bus master to perform data transfer without external address decoding or an external dynamic random access memory controller. In this example where sequential access is used, the integrated circuit is automatically increased by an external supply, and the initial memory address supplied by the bus master is accelerated, thereby accelerating the transmission. The bus master controller, and it allows virtual access to all the internal registers on the integrated circuit, and it allows static random access memory / dynamic random access memory controller on the chip to store Take external memory. These and other objects and advantages of the present invention will become more fully apparent from the description and the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of the chip structure on the system of the present invention; ____ -6- This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) ~ II I " ----- —F (Please read the precautions on the back before filling in this page) A7 _ B7 I ": Description of Invention ΰ ”printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs'-Figure 2 shows the integrated circuit of this invention and the connection to this A block diagram of pin connections between devices on a chip. Detailed description of the preferred example of the first embodiment. Referring first to FIG. 1, the wafer structure on a system of the present invention is generally described as 10. The integrated circuit 10 includes a 32-bit reduced instruction set calculation central processor 12 connected to a 32-bit internal bus 14. The CPU 1] is directly connected to the internal bus controller 16, which is sequentially connected to the bus 14 and to a bus map 18. The integrated circuit 10 further includes a local random access memory (static random access memory) 20, a combined command / data storage 22, and an external access port 24. In the preferred embodiment, the Jizhao circuit 10 attempts to connect to a liquid crystal display (LCD) and to the terminal, including a liquid crystal display controller to be connected to a liquid crystal display panel interface 28. An external bus controller 30 is provided and connected to a 26-bit external memory interface 32 and external chip selection 34. A plurality of configuration registers 36 are provided, and their functions will be described later. In the preferred embodiment, the configuration register 36 is located in the internal bus controller 16. A number of internal " peripheral devices " are located on the integrated circuit 10, and are connected to the internal sink 14, and include a universal asynchronous receiving and sending symbol (UART) 38, a parallel port 40, a Timer / counter 42, an interrupt controller 44, and a pulse width modulator (PWM) 46. An external bus master 48, also referred to here as an external device, is connected to the external memory interface 32, the external chip selection 34 and to an external memory 50. The external memory 50 may include static random access memory and dynamic random access memory ports to this point. Peripheral equipment, marked as 52, is connected to this paper standard is applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) tn · I {installed-- {please read the precautions on the back before filling this page) Book Economy Printed by the Ministry of Standards and Staff Employee Consumer Cooperatives Printed by the Ministry of Economic Affairs of the Central Standards Agency Employee Consumer Cooperatives A7 B7 V. Invention Description (5) External Memory Zhao Interface 3 2 and External Chip Selection 3 4 The external memory skull interface 32 and the external chip selection 34 are part of the external bus controller 30 in this preferred embodiment. Those skilled in the art will recognize objects with reference numbers 2 to 46 to form components of the integrated circuit 10, and objects with reference numbers greater than 46 are non-on-chip devices. In the preferred embodiment, the integrated circuit 10 is constructed as a 160-pin thin four-row flat-pack (TQFP) package. Referring now to FIG. 2, those who are particularly interested in the present invention will find that these pins are connected to an external bus master 48 and is a specific bus master demand (BREQ) for transmitting a demand signal. The bus master The device grant (BGR) is used to send an grant signal, send demand (xrEq), and send acknowledgement (XACK). The signal flow is represented by the arrow line connected to the integrated circuit 10, the external bus master 48, the dynamic random access memory 50, the static random access memory 5 and the peripheral devices 52. Preferably, the external memory interface 32 and the external chip selection 34 are substantially located in the external bus controller 30 of the preferred embodiment. The pin bus master control requirements and transmission requirements are related to this as a demand institution. When the pin bus master control grant and transfer confirmation are regarded as a grant institution. The data and / or commands will then circulate on the integrated circuit 10 and peripheral devices on the external memory bus as data, address and control functions are collectively marked as bus 5 4. For a detailed description of the foregoing, please refer to FIGS. 1 and 2 now, the central processing unit 12 allows the external bus master 48 to control the external memory interface 3 2 and use on-chip static random access memory / dynamic random The access memory controller is generally located in the internal bus controller j 6 to transmit data. The four signals identified above are used for Yuancheng external interface 32 control. Be aware of external busbars. This paper scale is applicable to China National Standards (CNS) A4 (210x297 public issue;) --------- 策 —-'(Please read the precautions on the back before filling this page)
、tT 321723 A7 B7 五、發明説明（6 ) 王控制器48必需爲外部記憶體5〇提供其本身晶片致及行位 址選擇/列位址選擇訊號，或其必須使用傳送需求/傳送確 涊以存取使用内部匯流排控制器i 6内靜態隨機存取記憶體 /動態隨機存取記憶體控制器的晶片上控制訊號。外部匯流 排王控制器4 8需求控制外部記憶體界面3 2以確定匯流排主 控需求接腳高，當中央處理機12完成任何現行匯流排操作 ，外部界面32將被釋放至外部匯流排主控器48及該匯流排 主控授與接腳將被驅動爲高。在外部匯流排主控器已完成 資料詢問或傳送，其確保匯流排主控需求接腳爲低及中央 處理機12確保匯流排主控器授與爲低，此表示該外部記憶 體界面已由外部匯流排控制器4 8釋放及該外部記憶體界面 現在中央處理機1 2的控制下。 當中央處理機1 2檢測到該匯流排主控需求爲高，其完成 電沭匯流排操作和確保匯流排主控器授與爲高，此容許外 部匯流排主控器48控制外部界面。所有晶片上組件將在外 部匯流排4 8的控制下，除了中央處理機i 2，其將在間置狀 態。在匯流排主控器授與由中央處理機維持爲高時，外部 匯流排主控器4 8將控制外部記憶體界面32。應瞭解雖然中 央處理機是在一間置模態’積體電路1〇將根據其程式化持 續更新該動態隨機存取記憶體庫，也當做是一更新機構。 當外部匯流排主控器4 8確保該傳送需求接腳爲高，及假 設匯流排主控器授與也被確認爲高，外部匯流排主控器48 可存取内部靜態隨機存取記憶體，窖藏器，暫存器，動態 隨機存取記憶體控制器和靜態隨機存取記憶體控制器。外 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） I I II - · --S策-- (請先閱讀背面之注意事項再填寫本頁) >?τ 經濟部中央標準局員工消費合作社印製 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（7 ) 邵匯流排主控器4 8提供位址，資料，讀/寫存取，及傳送 尺寸至積體電路10，其使用其晶片上控制器以完成該傳送 。外部醒流排主控器也需要積體電路10内部地追縱該傳送 位址’在位於内部匯流排控制器1 6的一記憶體映圖暫存器 内，及特別是在其間該等组態暫存器3 6之—内，因此減少 爲第一次傳送提供一外部位址在該需求上之需要。此包含 在此被备做一停止/起始機構以置放中央處理機12在一間 置模態同時容許外部設備48存取晶片上暫存器。 當積禮電路10檢測該傳送需求接腳被確定爲高，其以確 疋該傳送確認接腳爲高之形式提供一確認訊號，及閂鎖一 組態内該位址，資料和控制以由外部匯流排主控器4 8存取 。積體電路1 0可經由確定匯流排主控器授與低控制外部記 憶體界面32，此從控制積體電路10阻斷外部匯流排主控器 48。當該需求傳送被完成，積體電路1〇將驅動傳送確認爲 低’置放資料匯流排5 4在一讀操作及持續確定匯流排主控 授與爲低，於傳送需求爲高時，當傳送需求由外部匯流排 主控器48驅動爲低，積體電路10將確定匯流排主控器授與 爲咼’因而給予外部匯流排主控器48控制界面32。外部匯 流排主控器可經由驅動傳送需求爲高啓始另一傳送，或經 由釋放匯流排5 4，或驅動匯流排主控需求爲低。 當積體電路1 0在外部匯流排主控器4 8控制下，接腳η 〇E ’ nWE，及nBW是在高阻抗狀態，及驅動nCE/nCAS* nRAS爲不動作。當在此使用，一接腳前之"n "表示"非"。 nOE是外部記憶體和週邊設備之輸出致能，及容許外部記 (請先閲讀背面之注意事項再填寫本頁) 袈. 訂- -10- 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（8 ) 憶體和週邊設備驅動該資料匯流排。其確保在一讀操作爲 低及在一寫操作爲高。當在外部匯流排主控器48控制下， 其作用爲微控制器12!的輸出致能，其係被内嵌至中央處理 機1 2。nOE應由外部匯流排主控器4 8驅動爲低於一讀操作 及爲高於一寫操作。 nWE是外部記憶體和週邊設備的寫致能。在一寫作動， nWE被驅動爲低，及其在一讀作動與羅動爲高。當在外部 匯流排主控器4 8控制下，nWE應被驅動爲低於寫作動，及 在一讀作動爲高。 nCE/nCAS[5 ： 0 ]提供該晶片致能（CE)/行位址選擇（cAS) 容許直接連接至標準外部記憶體/週邊設備。該等接腳作動 如一 nCAS於界面至動態隨機存取記憶體50色及作動爲一 nCE 於界面至動態隨機存取記憶體5〇k或週邊設備52。該等接 腳由該系統設計者可完全程式化及可支撑數元組致能。 nCE在外部匯流排主控器4 8控制下是不作動，nCAS僅在一 更新操作爲作動，更新被程式化入該電路。nRAS提供列位 址選擇容許直接連接至動態隨機存取記憶體5〇1。nRAS於 外部匯流排主控器4 8控制下是不動作的。 接腳被指定爲A[25: 0]及D[15: 0]也是在一高阻抗 狀態於匯流排主控器授與爲高。A[25 : 0]指定26外部位 址匯流排接腳，及容許該内嵌微控制器以提供一 2 6數元位 址至外部記憶體和週邊設備。當在外部匯流排主控器4 8控 制下’一26數元位址被送至該内嵌微控制器。該位址的高 階6數元由一内部可程式化暫存器提供，位於組態暫存器 ____ -11 - 本矣氏張尺度適用中^^標準…^^以规格㈠⑴:^了公釐） ' (請先閲讀背面之注意事項再填寫本頁) 策 訂 經濟部中央標準局*C工消費合作社印製 3 21723 A7 B7 五、發明説明（9 ) 36内，給予該外部匯流排主控器完全存取該32數元位址空 間。 D[1 5 : 0 ]指定該16接腳外部16數元資料匯流排。當在 外部匯流排主控器4 8控制下，輸入資料被提供於一寫存取 内嵌微控制器12色。nBW是該數元組寬存取接腳。中央處理 機12提供一訊號至外部記憶體50及週邊設備52以標示該 資料傳送器的資料尺寸。 nBW可由一外部位址控制器使用以產生額外晶片/數元致 能。當在外部匯流排主控器4 8控制下，該外部匯流排主控 器標示該傳送尺寸。無論該作動控制器，中央處理機12或 外部匯流排主控器48，接腳nBW確定爲低則標示一數元傳 送器，及一高確定在接腳nBW則標示一半字元（16數元傳 送器）。 接腳nBB是該數元靴式啓動接腳，其將使用以爲該靴式 啓動記憶體於8數元或16數元間選擇。當積體電路1〇在外 部匯流排主控器48控制下，外部匯流排主控器48可提供其 本身位址至匯流排5 4上的微處理器12生，其中接腳nBB被確 定爲低，及該位址的高階6數元係由一内部可程式化暫存 器的提供’標示爲外邵匯流排主控器延伸暫存器（EBMER) 及位於組態暫存器36内。該外部匯流排主控器48也可要求 該内嵌微控制器以内部地追蹤該傳送器數元，其中接腳 nBB應被確定爲高。微控制器12注調整該内部位址爲由外部 匯流排主控器4 8 (nBW)所特定之該傳送器尺寸的一功能。 一外部匯流排主控器暫存器用以從外部匯流排主控器4 8 ί請先閲讀背面之注意事項再填寫本頁) 策· 訂、 TT 321723 A7 B7 V. Description of invention (6) The king controller 48 must provide its own chip and row address selection / column address selection signal to the external memory 50, or it must use the transmission demand / transmission confirmation To access the on-chip control signal using the static random access memory / dynamic random access memory controller in the internal bus controller i 6. The external bus king controller 4 8 needs to control the external memory interface 3 2 to determine the bus master demand pin is high, when the central processing unit 12 completes any current bus operation, the external interface 32 will be released to the external bus master The controller 48 and the bus master control grant pin will be driven high. The external bus master has completed the data query or transmission, which ensures that the bus master demand pin is low and the central processor 12 ensures that the bus master controller grant is low, which means that the external memory interface has been The external bus controller 48 is released and the external memory interface is now under the control of the central processor 12. When the central processing unit 12 detects that the bus master demand is high, it completes the power bus operation and ensures that the bus master controller grant is high, which allows the external bus master 48 to control the external interface. All on-chip components will be under the control of the external bus 48, except for the central processing unit i 2, which will be in an interposed state. When the bus master controller grant is maintained high by the central processor, the external bus master controller 48 will control the external memory interface 32. It should be understood that although the central processing unit is in a modal integrated circuit 10, it will continuously update the dynamic random access memory bank according to its programming, and it is also regarded as an updating mechanism. When the external bus master 48 ensures that the transmission demand pin is high, and assuming that the bus master grant is also confirmed to be high, the external bus master 48 can access the internal static random access memory , Cellar, temporary storage, dynamic random access memory controller and static random access memory controller. The size of the external paper is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) II II-· --S policy-(please read the precautions on the back before filling this page) >? Τ Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative A7 B7 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (7) Shao Busbar Controller 4 8 Provides address, data, read / write access, and transfer size to the product Circuit 10, which uses its on-chip controller to complete the transfer. The external bus master also needs to track the transmission address internally in the integrated circuit 10 'in a memory map register located in the internal bus controller 16 and especially during these groups State register 36, so it reduces the need to provide an external address for the first transfer on this demand. This includes being prepared here as a stop / start mechanism to place the CPU 12 in an interim mode while allowing external equipment 48 to access the on-chip scratchpad. When the Jail circuit 10 detects that the transmission demand pin is determined to be high, it provides a confirmation signal in the form of confirming that the transmission confirmation pin is high, and latches the address in the configuration, data and control by External bus master controller 48 access. The integrated circuit 10 can grant the low-control external memory interface 32 via the determined bus master, and the slave control integrated circuit 10 blocks the external bus master 48. When the demand transmission is completed, the integrated circuit 10 confirms that the drive transmission is low. The placement data bus 54 is in the first reading operation and continuously determines that the bus master grant is low. When the transmission demand is high, when The transmission demand is driven low by the external bus master 48, and the integrated circuit 10 will determine the grant of the bus master as a sibling and thus give the external bus master 48 the control interface 32. The external bus master can initiate another transmission via the drive transmission demand as high, or by releasing the bus 54 or drive the bus master demand as low. When the integrated circuit 10 is under the control of the external bus master 48, the pins ηE'nWE and nBW are in a high impedance state, and driving nCE / nCAS * nRAS is inactive. When used here, " n " before a pin means " not ". nOE is the output enable of external memory and peripheral devices, and allows external records (please read the notes on the back before filling out this page) 袈. Order--10- Printed by the Ministry of Economy Central Standards Bureau Employee Consumer Cooperative A7 B7 Five 3. Description of the invention (8) Memory and peripheral devices drive the data bus. It ensures that the first read operation is low and the first write operation is high. When controlled by the external bus master 48, it acts as an output enable for the microcontroller 12 !, which is embedded in the central processor 12. nOE should be driven by the external bus master 48 to below one read operation and above one write operation. nWE is the write enable of external memory and peripheral devices. During the first writing action, nWE is driven low, and the first reading action and pull action are high. When under the control of the external bus master 48, nWE should be driven below the writing action, and the first reading action is high. nCE / nCAS [5: 0] provides the chip enable (CE) / row address selection (cAS) to allow direct connection to standard external memory / peripheral devices. These pins act as an nCAS interface to the dynamic random access memory 50 colors and an nCE interface to the dynamic random access memory 50k or peripheral device 52. These pins are fully programmable by the system designer and can support tuples. nCE is not activated under the control of the external bus master 48. nCAS is only activated during an update operation, and the update is programmed into the circuit. nRAS provides column address selection to allow direct connection to dynamic random access memory 501. nRAS is inactive under the control of the external bus master 48. The pins designated as A [25: 0] and D [15: 0] are also high in the high impedance state granted by the bus master. A [25: 0] specifies 26 external address bus pins, and allows the embedded microcontroller to provide a 26-bit address to external memory and peripheral devices. When controlled by an external bus master 48, a 26-bit address is sent to the embedded microcontroller. The high-order 6 digits of this address are provided by an internal programmable register, which is located in the configuration register ____ -11-This scale is applicable ^^ Standard… ^^ With specifications㈠⑴: ^ 了 公)) (Please read the precautions on the back before filling in this page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs * C Industrial and Consumer Cooperatives 3 21723 A7 B7 V. Invention description (9) 36, given to the external bus master The controller has full access to the 32-bit address space. D [1 5: 0] specifies the 16-pin external 16-bit data bus. When under the control of the external bus master 48, the input data is provided to a write access embedded microcontroller 12 colors. nBW is the wide access pin of the tuple. The central processor 12 provides a signal to the external memory 50 and peripheral devices 52 to indicate the data size of the data transmitter. nBW can be used by an external address controller to generate additional chip / element enablement. When under the control of the external bus master 48, the external bus master indicates the transmission size. Regardless of the actuation controller, the central processing unit 12 or the external bus master 48, when pin nBW is determined to be low, it indicates a one-element transmitter, and if it is determined to be pin nBW, it indicates half of the character (16 digit Transmitter). Pin nBB is the digital boot boot pin, which will be used to select the boot boot memory between 8 or 16 digits. When the integrated circuit 10 is under the control of the external bus master 48, the external bus master 48 can provide its own address to the microprocessor 12 on the bus 54, where the pin nBB is determined as Low, and the high-order 6-digits of the address are provided by an internal programmable register 'marked as the external bus master extension register (EBMER) and located in the configuration register 36. The external bus master 48 may also require the embedded microcontroller to internally track the transmitter number, where pin nBB should be determined to be high. The microcontroller 12 notes that the internal address is a function of the transmitter size specified by the external bus master 48 (nBW). An external bus main controller register is used for external bus main controller 4 8 ί Please read the precautions on the back before filling this page) Policy · Order
經濟部中央標準局員工消費合作社印裝 A7 ^____B7_ 五、發明説明（10) 擴張位址從26數元至32數元，因此容許存取由中央處理機 提供的整體位址空間。該内部3 2數元位址係由增加6數元 的一數元延伸至接腳A[25 : 0]上該26數元位址所形成。 每次外部匯流排主控器4 8提供一外部位址及nBB被確定爲 低，積體電路1 〇經由結合於外部匯流排主控器位址及該外 部匯流排主控器延伸暫存器内發現之位址延伸捕獲該外部 位址及形成一32數元内部位址。當該存取被完成，積體電 路1 〇根據經由外部匯流排主控器4 8經由nBW特定的傳送尺 寸更新該新位址’以指定下一可定位位址位置。假如外部 匯流排主控器4 8係導引順序傳送，此結構容許積體電路i 〇 供給未來位址。這可由確定nBB爲高以在結果傳送下完成 ’其中積體電路10忽略該外部位址及使用其本身更新位址 以替代。該位址延伸起始被載入該外部匯流排主控器延伸 暫存器内，具有一"1 1 1 1 1 1 "邏輯値，容部外部匯流排主 控器4 8以存取包括系統和週邊設備暫存器的記憶體的較上 區域’包括該外部匯流排主控器延伸暫存器，局部靜態隨 機存取記憶體，窖藏器，及除外向量❶該外部匯流排:控 器延伸暫存器可由一儲存指令或由外部匯流排主控器48更 新。當外部匯流排主控器延伸暫存器被從"llllu"改變 ，該外部匯流排主控器48是不容許存取該外部匯流排主控 器暫存器延伸或記憶體較上區域。前述結構包含何被參^ 爲一自動位址增加裝置。 因此，一使用者或設計者可存取積體電路上任何暫存器 的内容。這可用於診斷，以決定積體電路1〇作動内任何特 (請先閲讀背面之注意事項再填寫本頁) s衣_ '訂Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 ^ ____ B7_ V. Description of the invention (10) The expansion of the address from 26 yuan to 32 yuan, thus allowing access to the entire address space provided by the central processing unit. The internal 32-bit address is formed by adding a 6-bit one to the 26-bit address on pin A [25: 0]. Each time the external bus master 48 provides an external address and nBB is determined to be low, the integrated circuit 10 is combined with the external bus master address and the external bus master extension register The internally discovered address extension captures the external address and forms a 32-bit internal address. When the access is completed, the integrated circuit 10 updates the new address according to the specific transmission size via the nBW via the external bus master 48 to specify the next addressable location. If the external bus master 48 is directed to transmit sequentially, this structure allows the integrated circuit i 〇 to supply future addresses. This can be done by determining that nBB is high to be delivered under the result. The integrated circuit 10 ignores the external address and uses its own update address instead. The address extension start is loaded into the extension register of the external bus master, with a " 1 1 1 1 1 1 " logic value, and the external bus master 48 to accommodate access The upper area of the memory including the system and peripheral registers' includes the external bus main controller extension register, local static random access memory, cellar, and exclusion vector ❶ the external bus: control The extension register can be updated by a store command or by the external bus controller 48. When the external bus master extension register is changed from " llllu ", the external bus master 48 does not allow access to the external bus master register extension or upper memory area. The foregoing structure includes the reference parameter ^ as an automatic address addition device. Therefore, a user or designer can access the contents of any register on the integrated circuit. This can be used for diagnosis to determine any special features in the operation of the integrated circuit 10 (please read the precautions on the back before filling out this page)
別點之-記錄器内容，用以程式化，此容許一使用 入一特定位址或資料至一暫存器，或用以測試，此容許一 設計者確認該一特定暫存器在作動時包括任何點的—既A 内容。 ^ 此系統可以是特別有用於積體電路丨0被使用爲_電荷耦 合設備（CCD)攝影機之部份，其中像素資料被從該電荷耦 合設備接收及被傳送至記憶體。該一傳送對一習用中斷系 統一般是太快而難以管理。無論如何，使用在此揭露的系 統，該起始位址可被提供，從積體電路1〇或從一些外部押 制’依該特定位址映圖而定，其將容許積體電路1〇在—高 速率傳送資料從該電荷耦合設備至記憶體。 门Other points-the contents of the recorder, for programming, this allows a use of a specific address or data into a register, or for testing, which allows a designer to confirm that a particular register is in operation Include any point-both A content. ^ This system can be particularly useful for integrated circuits that are used as part of a charge-coupled device (CCD) camera, where pixel data is received from the charge-coupled device and transferred to memory. This one-to-one transmission is generally too fast for a conventional interrupt system to manage. In any case, using the system disclosed here, the starting address can be provided, either from the integrated circuit 10 or from some external source 'depending on the specific address map, which will allow the integrated circuit 10. Transfer data at high speed from the charge-coupled device to the memory. door