JPS5577080A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS5577080A
JPS5577080A JP14936378A JP14936378A JPS5577080A JP S5577080 A JPS5577080 A JP S5577080A JP 14936378 A JP14936378 A JP 14936378A JP 14936378 A JP14936378 A JP 14936378A JP S5577080 A JPS5577080 A JP S5577080A
Authority
JP
Japan
Prior art keywords
column
activated
mosfets
decoders
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14936378A
Other languages
Japanese (ja)
Other versions
JPS6161199B2 (en
Inventor
Shoji Ishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14936378A priority Critical patent/JPS5577080A/en
Publication of JPS5577080A publication Critical patent/JPS5577080A/en
Publication of JPS6161199B2 publication Critical patent/JPS6161199B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To shorten a reset period while reducing a column-decoder pre-charge current, by pre-charging column address buffers and column decoders within the active period of a column address strobe. CONSTITUTION:Once a column address strobe is activated, address buffer control signals (phi1) and (phi2) are activated to pre-charge an address buffer, and consequently outputs corresponding to column address signals A0, A1... are generated while pre-charge signals of column decoders B1, B2... become ''0'', so that potentials at contacts 1-5 will be pre-charged corresponding to the output of the address buffer. Next, when control signal (phi3) is activated and MOSFETs Q12 and Q20 of a transfer gate are turned OFF, MOSFETs Q7-Q11 and Q16-Q15 forming a NOR circuit of decoders B1, B2... and column driving MOSFETs Q13 and Q21 are completely separated. Therefore, contacts 2 and 5 are pre-charged by a small current in a short time because of small floating capacity, so that a reset period in page mode will be shortened.
JP14936378A 1978-12-01 1978-12-01 Semiconductor circuit Granted JPS5577080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14936378A JPS5577080A (en) 1978-12-01 1978-12-01 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14936378A JPS5577080A (en) 1978-12-01 1978-12-01 Semiconductor circuit

Publications (2)

Publication Number Publication Date
JPS5577080A true JPS5577080A (en) 1980-06-10
JPS6161199B2 JPS6161199B2 (en) 1986-12-24

Family

ID=15473492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14936378A Granted JPS5577080A (en) 1978-12-01 1978-12-01 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS5577080A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60115094A (en) * 1983-11-16 1985-06-21 Fujitsu Ltd Dynamic random access memory device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02148392U (en) * 1989-05-19 1990-12-17

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287329A (en) * 1975-12-29 1977-07-21 Mostek Corp Mosfet integrated circuit chip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287329A (en) * 1975-12-29 1977-07-21 Mostek Corp Mosfet integrated circuit chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60115094A (en) * 1983-11-16 1985-06-21 Fujitsu Ltd Dynamic random access memory device
JPH0320836B2 (en) * 1983-11-16 1991-03-20 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6161199B2 (en) 1986-12-24

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