JPS5634185A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5634185A
JPS5634185A JP10892679A JP10892679A JPS5634185A JP S5634185 A JPS5634185 A JP S5634185A JP 10892679 A JP10892679 A JP 10892679A JP 10892679 A JP10892679 A JP 10892679A JP S5634185 A JPS5634185 A JP S5634185A
Authority
JP
Japan
Prior art keywords
line
cell
memory information
precharge
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10892679A
Other languages
Japanese (ja)
Inventor
Toshimoto Suzuki
Kazuki Yoshitake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10892679A priority Critical patent/JPS5634185A/en
Publication of JPS5634185A publication Critical patent/JPS5634185A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

PURPOSE:To simplify the sense circuit, by reducing the power consumption by precharge, by discriminating the memory information of cell with the potential state through the precharge to one data line. CONSTITUTION:The cell 7 is connected to the data lines 5, 6 and the address line 10, the lines 5, 6 are connected to the sense circuit 2 and the link circuit 11, and address is fed to the line 10 from the address decoder circuit 9. At the readout of memory information of the cell 7, when the signal PG is fed to the precharge line 4, the line 6 is at VDD level and the data output line 1 is at low level. When the memory information of the cell 7 is at ''1'', the line 6 is not discharged, but holds the VDD level, and the line 1 remains at low level. Thus, the readout of memory information can be made by precharging one data line.
JP10892679A 1979-08-27 1979-08-27 Memory circuit Pending JPS5634185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10892679A JPS5634185A (en) 1979-08-27 1979-08-27 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10892679A JPS5634185A (en) 1979-08-27 1979-08-27 Memory circuit

Publications (1)

Publication Number Publication Date
JPS5634185A true JPS5634185A (en) 1981-04-06

Family

ID=14497150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10892679A Pending JPS5634185A (en) 1979-08-27 1979-08-27 Memory circuit

Country Status (1)

Country Link
JP (1) JPS5634185A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52107736A (en) * 1976-03-08 1977-09-09 Toshiba Corp Mos random access memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52107736A (en) * 1976-03-08 1977-09-09 Toshiba Corp Mos random access memory

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