JPS5574172A - Interpolation type mos transistor - Google Patents

Interpolation type mos transistor

Info

Publication number
JPS5574172A
JPS5574172A JP14701078A JP14701078A JPS5574172A JP S5574172 A JPS5574172 A JP S5574172A JP 14701078 A JP14701078 A JP 14701078A JP 14701078 A JP14701078 A JP 14701078A JP S5574172 A JPS5574172 A JP S5574172A
Authority
JP
Japan
Prior art keywords
layers
film
type
layer
overlaid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14701078A
Other languages
Japanese (ja)
Inventor
Shinobu Fukunaga
Isao Okura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14701078A priority Critical patent/JPS5574172A/en
Publication of JPS5574172A publication Critical patent/JPS5574172A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance high-frequency characteristic by interposing n-layer in the FET areas of p<->-type and n<-->-type channels to prevent punch-through and latch-up generation. CONSTITUTION:As ions are injected into a p<->-type Si substrate 1a to form n-layer 12 which is overlaid with an addition-free n<--> epitaxial layer 13, and the layers 13, 12 are anisotropically etched. Then, the substrate 1a is overlaid at the specified locations with SiO2 film 16a, Si3N4 film 17a, The layer 13 also selectively overlaid with SiO2 film 16b and Si3N4 film 17b. Using mask of resist 18, p-type invertion-prevention layer 14 is formed. Thereafter, oxide film 7 is formed by heat treatment, then the SiO2 film and Si3N4 film are etched away. On each of new gate oxide film 5a, and 5b, n-type polycrystalline silicon gate layers 6a, 6b, and resist films 19a, 19b are formed which is followed by B ion injection to form p<+>-layers 4a, 4b, and p- layers 20a, 20b. Using resist mask 21, P ion is injected to transform the layers 20a, 20b to n<+>- layers 3a, 3b. Then, general procedures follow to provide a CMOS device having a very good operation properties.
JP14701078A 1978-11-27 1978-11-27 Interpolation type mos transistor Pending JPS5574172A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14701078A JPS5574172A (en) 1978-11-27 1978-11-27 Interpolation type mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14701078A JPS5574172A (en) 1978-11-27 1978-11-27 Interpolation type mos transistor

Publications (1)

Publication Number Publication Date
JPS5574172A true JPS5574172A (en) 1980-06-04

Family

ID=15420504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14701078A Pending JPS5574172A (en) 1978-11-27 1978-11-27 Interpolation type mos transistor

Country Status (1)

Country Link
JP (1) JPS5574172A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571609A (en) * 1980-06-16 1986-02-18 Tokyo Shibaura Denki Kabushiki Kaisha Stacked MOS device with means to prevent substrate floating
JPS61501736A (en) * 1984-03-29 1986-08-14 ヒユ−ズ・エアクラフト・カンパニ− Latch-up resistant CMOS structure for VLSI
US4635089A (en) * 1981-10-28 1987-01-06 Kabushiki Kaisha Daini Seikosha MIS-integrated semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039882A (en) * 1973-07-11 1975-04-12
JPS5162676A (en) * 1974-11-29 1976-05-31 Hitachi Ltd
JPS5310984A (en) * 1976-07-17 1978-01-31 Mitsubishi Electric Corp Complementary type mos integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039882A (en) * 1973-07-11 1975-04-12
JPS5162676A (en) * 1974-11-29 1976-05-31 Hitachi Ltd
JPS5310984A (en) * 1976-07-17 1978-01-31 Mitsubishi Electric Corp Complementary type mos integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571609A (en) * 1980-06-16 1986-02-18 Tokyo Shibaura Denki Kabushiki Kaisha Stacked MOS device with means to prevent substrate floating
US4635089A (en) * 1981-10-28 1987-01-06 Kabushiki Kaisha Daini Seikosha MIS-integrated semiconductor device
JPS61501736A (en) * 1984-03-29 1986-08-14 ヒユ−ズ・エアクラフト・カンパニ− Latch-up resistant CMOS structure for VLSI

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